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參數(shù)資料
| 型號： | AD817ARZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 2/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OPAMP LP HS 8-SOIC |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 應(yīng)用： | 通用 |
| 電路數(shù)： | 1 |
| -3db帶寬： | 50MHz |
| 轉(zhuǎn)換速率： | 350 V/µs |
| 電流 - 電源： | 7mA |
| 電流 - 輸出 / 通道： | 50mA |
| 電壓 - 電源，單路/雙路(±)： | 5 V ~ 36 V，±2.5 V ~ 18 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SO |
| 包裝： | 帶卷 (TR) |
REV. B
–10–
AD817
OFFSET NULLING
The input offset voltage of the AD817 is inherently very low.
However, if additional nulling is required, the circuit shown in
Figure 32 can be used. The null range of the AD817 in this con-
figuration is
±15 mV.
AD817 SETTLING TIME
Settling time is comprised primarily of two regions. The first is
the slew time in which the amplifier is overdriven, where the
output voltage rate of change is at its maximum. The second is
the linear time period required for the amplifier to settle to
within a specified percent of the final value.
0.10
0.20
0.15
0.05
0
4
6
10
8
2
0
350
400
300
250
200
150
100
50
SETTLING
TIME
TO
%
OF
FINAL
VALUE
OUTPUT
SWING
–
Volts
Figure 33. Settling Time in ns 0 V to +10 V
Measuring the rapid settling time of AD817 (45 ns to 0.1% and
70 ns to 0.01%–10 V step) requires applying an input pulse with
a very fast edge and an extremely flat top. With the AD817 con-
figured in a gain of –1, a clamped false summing junction re-
sponds when the output error is within the sum of two diode
voltages (1 volt). The signal is then amplified 20 times by a
clamped amplifier whose output is connected directly to a sam-
pling oscilloscope. Figures 33 and 34 show the settling time of
the AD817, with a 10 volt step applied.
0.05
0
0.20
0.10
0.15
–10
–6
–4
0
–2
–8
0
350
400
300
250
200
150
100
50
SETTLING
TIME
TO
%
OF
FINAL
VALUE
OUTPUT
SWING
–
Volts
Figure 34. Settling Time in ns 0 V to –10 V
AD829
100
0.47
F
0.01
F
+V
S
0.47
F
0.01
F
–V
S
SHORT, DIRECT
CONNECTION TO
TEKTRONIX TYPE 11402
OSCILLOSCOPE PREAMP
INPUT SECTION
SETTLING
OUTPUT
2
×
HP2835
ERROR AMPLIFIER
V
ERROR OUTPUT × 10
2
×
HP2835
1.9k
100
AD817
0.01
F
+V
S
0.01
F
2.2
F
–V
S
2.2
F
10pF
SCOPE PROBE
CAPACITANCE
TEKTRONIX P6201
FET PROBE TO
TEKTRONIX TYPE
11402
OSCILLOSCOPE
PREAMP INPUT
SECTION
500
5–18pF
DEVICE
UNDER
TEST
NOTE:
USE CIRCUIT BOARD
WITH GROUND PLANE
FALSE
SUMMING
NODE
NULL
ADJUST
1k
100
1k
50
COAX
CABLE
TTL LEVEL
SIGNAL
GENERATOR
50Hz
OUTPUT
7, 8
0 TO
±10V
POWER
SUPPLY
EI&S
DL1A05GM
MERCURY RELAY
ERROR
SIGNAL
OUTPUT
500
50
6
3
2
4
15pF
1M
7
6
3
2
4
5
13
2
1, 14
DIGITAL
GROUND
ANALOG
GROUND
7
Figure 35. Settling Time Test Circuit
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