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參數(shù)資料
型號(hào)： AD8202YRMZ-RL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 7/20頁(yè)
文件大?。?/td> 0K
描述： IC AMP DIFF 50KHZ 8MSOP
產(chǎn)品培訓(xùn)模塊： Current Sense Amplifiers
標(biāo)準(zhǔn)包裝： 3,000
放大器類(lèi)型： 差分
電路數(shù)： 1
轉(zhuǎn)換速率： 0.28 V/µs
增益帶寬積： 50kHz
電流 - 輸入偏壓： 40nA
電壓 - 輸入偏移： 2000µV
電流 - 電源： 250µA
電壓 - 電源，單路/雙路(±)： 3.5 V ~ 12 V
工作溫度： -40°C ~ 125°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 8-TSSOP，8-MSOP（0.118"，3.00mm 寬）
供應(yīng)商設(shè)備封裝： 8-MSOP
包裝： 帶卷 (TR)
Data Sheet
AD8202
Rev. H | Page 15 of 20
GAIN TRIM
Figure 45 shows a method for incremental gain trimming by
using a trim potentiometer and external resistor, REXT.
The following approximation is useful for small gain ranges:
ΔG ≈ (10 M/REXT)%
Thus, the adjustment range is ±2% for REXT = 5 M; ±10% for
REXT = 1 M, and so on.
5V
OUT
REXT
GAIN TRIM
20k
MIN
VCM
VDIFF
2
VDIFF
2
NC = NO CONNECT
GND
NC
–IN
+IN
A1
+VS
A2
OUT
AD8202
04981-018
Figure 45. Incremental Gain Trim
Internal Signal Overload Considerations
When configuring gain for values other than 20, the maxi-
mum input voltage with respect to the supply voltage and
ground must be considered because either the preamplifier
or the output buffer reaches its full-scale output (approximately
VS 0.2 V) with large differential input voltages. The input of
the AD8202 is limited to (VS 0.2)/10 for overall gains ≤ 10
because the preamplifier, with its fixed gain of ×10, reaches its full-
scale output before the output buffer. For gains greater than 10, the
swing at the buffer output reaches its full scale first and limits the
AD8202 input to (VS 0.2)/G, where G is the overall gain.
LOW-PASS FILTERING
In many transducer applications, it is necessary to filter
the signal to remove spurious high frequency components
including noise, or to extract the mean value of a fluctuating
signal with a peak-to-average ratio (PAR) greater than unity.
For example, a full-wave rectified sinusoid has a PAR of 1.57,
a raised cosine has a PAR of 2, and a half-wave sinusoid has a
PAR of 3.14. Signals having large spikes can have PARs of 10
or more.
When implementing a filter, the PAR should be considered
so that the output of the AD8202 preamplifier (A1) does not clip
before A2 because this nonlinearity would be averaged
and appear as an error at the output. To avoid this error,
both amplifiers should clip at the same time. This condition
is achieved when the PAR is no greater than the gain of the
second amplifier (2 for the default configuration). For example,
if a PAR of 5 is expected, the gain of A2 should be increased to 5.
Low-pass filters can be implemented in several ways by using the
AD8202. In the simplest case, a single-pole filter (20 dB/decade)
is formed when the output of A1 is connected to the input of
A2 via the internal 100 k resistor by tying Pin 3 and Pin 4
and adding a capacitor from this node to ground, as shown in
Figure 46. If a resistor is added across the capacitor to lower the
gain, the corner frequency increases; it should be calculated using
the parallel sum of the resistor and 100 k.
5V
VCM
VDIFF
2
VDIFF
2
NC = NO CONNECT
C
GND
NC
–IN
+IN
A1
+VS
A2
OUT
AD8202
04981-019
OUTPUT
fC =
1
2
πC105
C IN FARADS
Figure 46. Single-Pole, Low-Pass Filter Using the Internal 100 k Resistor
If the gain is raised using a resistor, as shown in Figure 44, the
corner frequency is lowered by the same factor as the gain is
raised. Thus, using a resistor of 200 k (for which the gain
would be doubled), the corner frequency is now 0.796 Hz/F
(0.039 F for a 20 Hz corner frequency).
5V
VCM
VDIFF
2
VDIFF
2
NC = NO CONNECT
C
GND
NC
–IN
+IN
A1
+VS
A2
OUT
AD8202
04981-020
OUT
C
255k
fC(Hz) = 1/C(F)
Figure 47. 2-Pole, Low-Pass Filter
A 2-pole filter (with a roll-off of 40 dB/decade) can be
implemented using the connections shown in Figure 47. This is a
Sallen-Key form based on a ×2 amplifier. It is useful to remember
that a 2-pole filter with a corner frequency f2 and a 1-pole filter
with a corner at f1 have the same attenuation at the frequency
(f22/f1). The attenuation at that frequency is 40 log (f2/f1), which is
illustrated in Figure 48. Using the standard resistor value shown
and equal capacitors (see Figure 47), the corner frequency is
conveniently scaled at 1 Hz/F (0.05 F for a 20 Hz corner).
A maximally flat response occurs when the resistor is lowered to
196 k and the scaling is then 1.145 Hz/F. The output offset
is raised by approximately 5 mV (equivalent to 250 V at the
input pins).
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