40log (f2/f1
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� AD8203YRZ-R7
寤犲晢锛� Analog Devices Inc
鏂囦欢闋佹暩(sh霉)锛� 8/20闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC AMP DIFF 60KHZ 8SOIC
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 1,000
鏀惧ぇ鍣ㄩ鍨嬶細 宸垎
闆昏矾鏁�(sh霉)锛� 1
杞�(zhu菐n)鎻涢€熺巼锛� 0.330 V/µs
澧炵泭甯跺绌嶏細 60kHz
闆绘祦 - 杓稿叆鍋忓锛� 40nA
闆诲 - 杓稿叆鍋忕Щ锛� 1000µV
闆绘祦 - 闆绘簮锛� 250µA
闆诲 - 闆绘簮锛屽柈璺�/闆欒矾(±)锛� 3.5 V ~ 12 V
宸ヤ綔婧害锛� -40°C ~ 125°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 8-SOIC锛�0.154"锛�3.90mm 瀵級
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 8-SO
鍖呰锛� 甯跺嵎 (TR)
AD8203
Data Sheet
Rev. D | Page 16 of 20
40log (f2/f1)
f1
ATTENUATION
f2
f22/f1
FREQUENCY
A 1-POLE FILTER, CORNER f1, AND
A 2-POLE FILTER, CORNER f2, HAVE
THE SAME ATTENUATION 鈥�40log (f2/f1)
AT FREQUENCY f22/f1
20dB/DECADE
40dB/DECADE
05013-021
Figure 48. Comparative Responses of 1-Pole and 2-Pole Low-Pass Filters
HIGH LINE CURRENT SENSING WITH LPF AND
GAIN ADJUSTMENT
Figure 49 is another refinement of Figure 2, including gain
adjustment and low-pass filtering.
GND
NC
鈥揑N
+IN
A1
+VS
A2
OUT
AD8203
5V
INDUCTIVE
LOAD
POWER
DEVICE
4-TERM
SHUNT
CLAMP
DIODE
BATTERY
14V
NC = NO CONNECT
COMMON
05013-022
C
OUT
4V/AMP
5% CALIBRATION RANGE
fC(Hz) = 0.767Hz/C(F)
(0.22
F FOR f
C = 3.6Hz)
VOS/IB
NULL
133k
20k
Figure 49. High Line Current Sensor Interface;
Gain = 脳40, Single-Pole Low-Pass Filter
A power device that is either on or off controls the current in
the load. The average current is proportional to the duty cycle
of the input pulse and is sensed by a small value resistor. The
average differential voltage across the shunt is typically 100 mV,
although its peak value is higher by an amount that depends on
the inductance of the load and the control frequency. The
common-mode voltage, conversely, extends from roughly 1 V
above ground for the on condition to about 1.5 V above the
battery voltage for the off condition. The conduction of the
clamping diode regulates the common-mode potential applied
to the device. For example, a battery spike of 20 V may result in
an applied common-mode potential of 21.5 V to the input of
the devices.
To produce a full-scale output of 4 V, a gain 脳40 is used, adjust-
able by 卤5% to absorb the tolerance in the shunt. There is
sufficient headroom to allow 10% overrange (to 4.4 V). The
roughly triangular voltage across the sense resistor is averaged
by a 1-pole low-pass filter, shown in Figure 49, set with a corner
frequency of 3.6 Hz, which provides about 30 dB of attenuation
at 100 Hz. A higher rate of attenuation can be obtained using a
2-pole filter with fC = 20 Hz, as shown in Figure 50. Although
this circuit uses two separate capacitors, the total capacitance is
less than half that needed for the 1-pole filter.
GND
NC
鈥揑N
+IN
A1
+VS
A2
OUT
AD8203
5V
INDUCTIVE
LOAD
POWER
DEVICE
4-TERM
SHUNT
CLAMP
DIODE
BATTERY
14V
NC = NO CONNECT
COMMON
05013-023
fC(Hz) = 1/C(F)
(0.05
F FOR f
C = 20Hz)
C
OUTPUT
93k
C
301k
50k
Figure 50. 2-Pole Low-Pass Filter
DRIVING CHARGE REDISTRIBUTION ADCS
When driving CMOS ADCs, such as those embedded in popu-
lar microcontrollers, the charge injection (螖Q) can cause a
significant deflection in the output voltage of the AD8203.
Though generally of short duration, this deflection may persist
until after the sample period of the ADC has expired due to the
relatively high open-loop output impedance (21 k) of the
AD8203. Including an R-C network in the output can signifi-
cantly reduce the effect. The capacitor helps to absorb the
transient charge, effectively lowering the high frequency output
impedance of the AD8203. For these applications, the output
signal should be taken from the midpoint of the
RLAG to CLAG combination, as shown in Figure 51.
Since the perturbations from the analog-to-digital converter are
small, the output impedance of the AD8203 appears to be low. The
transient response, therefore, has a time constant governed by the
product of the two LAG components, CLAG 脳 RLAG. For the values
shown in Figure 51, this time constant is programmed at approxi-
mately 10 s. Therefore, if samples are taken at several tens of
microseconds or more, there is negligible charge stack-up.
+IN
鈥揑N
10k
10k
AD8203
5V
R
LAG
1k
C
LAG
0.01
F
MICROPROCESSOR
A/D
A2
2
4
7
5
05013-024
Figure 51. Recommended Circuit for Driving CMOS A/D
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