Placing a resistor across the RG terminals" />
參數(shù)資料
型號(hào): AD8220WARMZ
廠商: Analog Devices Inc
文件頁數(shù): 13/28頁
文件大?。?/td> 0K
描述: IC AMP INST JFET R-R 15MA 8MSOP
標(biāo)準(zhǔn)包裝: 50
放大器類型: 儀表
電路數(shù): 1
輸出類型: 滿擺幅
轉(zhuǎn)換速率: 2 V/µs
-3db帶寬: 1.5MHz
電流 - 輸入偏壓: 25pA
電壓 - 輸入偏移: 250µV
電流 - 電源: 750µA
電流 - 輸出 / 通道: 15mA
電壓 - 電源,單路/雙路(±): 4.5 V ~ 36 V,±2.25 V ~ 18 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 8-TSSOP,8-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 8-MSOP
包裝: 管件
AD8220
Rev. B | Page 20 of 28
GAIN SELECTION
Placing a resistor across the RG terminals sets the AD8220 gain,
which can be calculated by referring to Table 5 or by using the
gain equation
1
4
.
49
G
RG
Table 5. Gains Achieved Using 1% Resistors
1% Standard Table Value of RG (Ω)
Calculated Gain
49.9 k
1.990
12.4 k
4.984
5.49 k
9.998
2.61 k
19.93
1.00 k
50.40
499
100.0
249
199.4
100
495.0
49.9
991.0
The AD8220 defaults to G = 1 when no gain resistor is used.
Gain accuracy is determined by the absolute tolerance of RG.
The TC of the external gain resistor increases the gain drift of
the instrumentation amplifier. Gain error and gain drift are kept
to a minimum when the gain resistor is not used.
LAYOUT
Careful board layout maximizes system performance. In
applications that need to take advantage of the low input bias
current of the AD8220, avoid placing metal under the input path
to minimize leakage current. To maintain high CMRR over
frequency, lay out the input traces symmetrically and lay out the
traces of the RG resistor symmetrically. Ensure that the traces
maintain resistive and capacitive balance; this holds for additional
PCB metal layers under the input and RG pins. Traces from the
gain setting resistor to the RG pins should be kept as short as
possible to minimize parasitic inductance. An example layout is
shown in Figure 57 and Figure 58. To ensure the most accurate
output, the trace from the REF pin should either be connected to
the AD8220 local ground (see Figure 59) or connected to a
voltage that is referenced to the AD8220 local ground.
Common-Mode Rejection Ratio (CMRR)
The AD8220 has high CMRR over frequency giving it greater
immunity to disturbances, such as line noise and its associated
harmonics, in contrast to typical in-amps whose CMRR falls off
around 200 Hz. These in-amps often need common-mode
filters at the inputs to compensate for this shortcoming. The
AD8220 is able to reject CMRR over a greater frequency range,
reducing the need for input common-mode filtering.
A well-implemented layout helps to maintain the high CMRR
over frequency of the AD8220. Input source impedance and
capacitance should be closely matched. In addition, source
resistance and capacitance should be placed as close to the
inputs as possible.
Grounding
The output voltage of the AD8220 is developed with respect to
the potential on the reference terminal. Care should be taken to
tie REF to the appropriate local ground (see Figure 59).
In mixed-signal environments, low level analog signals need to
be isolated from the noisy digital environment. Many ADCs
have separate analog and digital ground pins. Although it is
convenient to tie both grounds to a single ground plane, the
current traveling through the ground wires and PC board can
cause a large error. Therefore, separate analog and digital
ground returns should be used to minimize the current flow
from sensitive points to the system ground.
03579-
101
Figure 57. Example Layout—Top Layer of the AD8220 Evaluation Board
03579-
102
Figure 58. Example Layout—Bottom Layer of the AD8220 Evaluation Board
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