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| 型號： | AD824AR-14 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OPAMP JFET R-R 2MHZ LP 14SOIC |
| 標準包裝： | 56 |
| 放大器類型： | J-FET |
| 電路數(shù)： | 4 |
| 輸出類型： | 滿擺幅 |
| 轉(zhuǎn)換速率： | 2 V/µs |
| 增益帶寬積： | 2MHz |
| -3db帶寬： | 2MHz |
| 電流 - 輸入偏壓： | 4pA |
| 電壓 - 輸入偏移： | 500µV |
| 電流 - 電源： | 560µA |
| 電流 - 輸出 / 通道： | 12mA |
| 電壓 - 電源，單路/雙路(±)： | 3 V ~ 30 V，±1.5 V ~ 15 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-SOIC |
| 包裝： | 管件 |
REV. C
AD824
–11–
A current-limiting resistor should be used in series with the
input of the AD824 if there is a possibility of the input voltage
exceeding the positive supply by more than 300 mV or if an
input voltage will be applied to the AD824 when
±VS = 0. The
amplifier will be damaged if left in that condition for more than
10 seconds. A 1 k
W resistor allows the amplifier to withstand up
to 10 V of continuous overvoltage and increases the input volt-
age noise by a negligible amount.
Input voltages less than –VS are a completely different story.
The amplifier can safely withstand input voltages 20 V below
the minus supply voltage as long as the total voltage from the
positive supply to the input terminal is less than 36 V. In addition,
the input stage typically maintains picoamp level input currents
across that input voltage range.
OUTPUT CHARACTERISTICS
The AD824’s unique bipolar rail-to-rail output stage swings
within 15 mV of the positive and negative supply voltages. The
AD824’s approximate output saturation resistance is 100
W for
both sourcing and sinking. This can be used to estimate output
saturation voltage when driving heavier current loads. For
instance, the saturation voltage will be 0.5 V from either supply
with a 5 mA current load.
For load resistances over 20 k
W, the AD824’s input error
voltage is virtually unchanged until the output voltage is driven
to 180 mV of either supply.
If the AD824’s output is overdriven so as to saturate either of
the output devices, the amplifier will recover within 2
ms of its
input returning to the amplifier’s linear operating region.
Direct capacitive loads will interact with the amplifier’s effective
output impedance to form an additional pole in the amplifier’s
feedback loop, which can cause excessive peaking on the pulse
response or loss of stability. Worst case is when the amplifier is
used as a unity gain follower. TPC 4 and 6 show the AD824’s
pulse response as a unity gain follower driving 220 pF. Configu-
rations with less loop gain, and as a result less loop bandwidth,
will be much less sensitive to capacitance load effects. Noise
gain is the inverse of the feedback attenuation factor provided
by the feedback network in use.
Figure 3 shows a method for extending capacitance load drive
capability for a unity gain follower. With these component val-
ues, the circuit will drive 5,000 pF with a 10% overshoot.
VOUT
VIN
1/4
AD824
–VS
+VS
20k
20pF
0.01 F
8
4
100
CL
Figure 3. Extending Unity Gain Follower Capacitive Load
Capability Beyond 350 pF
APPLICATION NOTES
INPUT CHARACTERISTICS
In the AD824, n-channel JFETs are used to provide a low
offset, low noise, high impedance input stage. Minimum input
common-mode voltage extends from 0.2 V below –VS to 1 V less
than +VS. Driving the input voltage closer to the positive rail will
cause a loss of amplifier bandwidth.
The AD824 does not exhibit phase reversal for input voltages
up to and including +VS. Figure 2a shows the response of an
AD824 voltage follower to a 0 V to 5 V (+VS) square wave input.
The input and output are superimposed. The output tracks the
input up to +VS without phase reversal. The reduced bandwidth
above a 4 V input causes the rounding of the output wave form.
For input voltages greater than +VS, a resistor in series with
the AD824’s noninverting input will prevent phase reversal at
the expense of greater input voltage noise. This is illustrated in
Figure 2b.
10
0%
100
90
1V
10s
1V
10
0%
100
90
1V
2s
1V
GND
+VS
+5V
RP
VOUT
VIN
Figure 2. (a) Response with RP = 0; VIN from 0 to +VS
(b) VIN = 0 to + VS + 200 m V
VOUT = 0 to + VS
RP = 49.9 k
W
Since the input stage uses n-channel JFETs, input current
during normal operation is positive; the current flows out from
the input terminals. If the input voltage is driven more positive
than +VS – 0.4 V, the input current will reverse direction as
internal device junctions become forward biased. This is
illustrated in TPC 8.
(b)
(a)
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