VS
參數(shù)資料
型號(hào)： AD8251ARMZ
廠(chǎng)商： Analog Devices Inc
文件頁(yè)數(shù)： 9/24頁(yè)
文件大?。?/td> 0K
描述： IC AMP INST ICMOS LDRIFT 10MSOP
標(biāo)準(zhǔn)包裝： 50
系列： iCMOS®
放大器類(lèi)型： 儀表
電路數(shù)： 1
轉(zhuǎn)換速率： 30 V/µs
-3db帶寬： 10MHz
電流 - 輸入偏壓： 5nA
電壓 - 輸入偏移： 70µV
電流 - 電源： 4.1mA
電流 - 輸出 / 通道： 37mA
電壓 - 電源，單路/雙路(±)： 10 V ~ 30 V，±5 V ~ 15 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 10-TFSOP，10-MSOP（0.118"，3.00mm 寬）
供應(yīng)商設(shè)備封裝： 10-MSOP
包裝： 管件
AD8251
Rev. B | Page 17 of 24
Table 5. Truth Table Logic Levels for Transparent Gain Mode
WR
A1
A0
Gain
VS
Low
1
VS
Low
High
2
VS
High
Low
4
VS
High
8
Latched Gain Mode
Some applications have multiple programmable devices such as
multiplexers or other programmable gain instrumentation
amplifiers on the same PCB. In such cases, devices can share a
data bus. The gain of the AD8251 can be set using WR as a latch,
allowing other devices to share A0 and A1.
shows a
schematic using this method, known as latched gain mode. The
AD8251 is in this mode when
WR is held at logic high or logic
low, typically 5 V and 0 V, respectively. The voltages on A0 and A1
are read on the downward edge of the WR signal as it transitions
from logic high to logic low. This latches in the logic levels on
A0 and A1, resulting in a gain change. See the truth table in
for more information on these gain changes.
+15V
–15V
A0
A1
WR
+IN
–IN
10
μF0.1F
10
μF0.1F
DGND
REF
AD8251
A0
A1
WR
+5V
0V
G = PREVIOUS
STATE
G = 8
+
–
NOTE:
1. ON THE DOWNWARD EDGE OF WR, AS IT TRANSITIONS
FROM LOGIC HIGH TO LOGIC LOW, THE VOLTAGES ON A0
AND A1 ARE READ AND LATCHED IN, RESULTING IN A
GAIN CHANGE. IN THIS EXAMPLE, THE GAIN SWITCHES TO G = 8.
06
28
7-
05
2
Figure 53. Latched Gain Mode, G = 8
Table 6. Truth Table Logic Levels for Latched Gain Mode
WR
A1
A0
Gain
High to low
Low
Change to 1
High to low
Low
High
Change to 2
High to low
High
Low
Change to 4
High to low
High
Change to 8
Low to low
No change
Low to high
No change
High to high
No change
1 X = don’t care.
On power-up, the AD8251 defaults to a gain of 1 when in latched
gain mode. In contrast, if the AD8251 is configured in transparent
gain mode, it starts at the gain indicated by the voltage levels on
A0 and A1 at power-up.
Timing for Latched Gain Mode
In latched gain mode, logic levels at A0 and A1 must be held for
a minimum setup time, tSU, before the downward edge of WR
latches in the gain. Similarly, they must be held for a minimum
hold time of tHD after the downward edge of WR to ensure that
the gain is latched in correctly. After tHD, A0 and A1 can change
logic levels, but the gain does not change (until the next
downward edge of WR). The minimum duration that WR can
be held high is t WR-HIGH, and the minimum duration that WR
can be held low is t WR-LOW. Digital timing specifications are
listed in
The time required for a gain change is
dominated by the settling time of the amplifier. A timing
diagram is shown in
.
When sharing a data bus with other devices, logic levels applied
to those devices can potentially feed through to the output of
the AD8251. Feedthrough can be minimized by decreasing the
edge rate of the logic signals. Furthermore, careful layout of the
PCB also reduces coupling between the digital and analog portions
of the board. Pull-up or pull-down resistors should be used to
provide a well-defined voltage at the A0 and A1 pins.
A0, A1
WR
tSU
tHD
tWR-HIGH
tWR-LOW
0
62
87
-0
53
Figure 54. Timing Diagram for Latched Gain Mode
相關(guān)PDF資料
PDF描述
UY2-PK50 SCOTCHLOK BUTT 19-26AWG 50PCS
TSW-149-07-L-D CONN HEADER 98POS .100" DL GOLD
AD8421BRZ IC OP AMP INSTRUMENTATION 8SOIC
SL1411A250SM GAS TUBE GDT 10KA 250V SMD
PEC30DGBN CONN HEADER .100 DUAL R/A 60POS
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD8251ARMZ-R7 功能描述:IC AMP INST ICMOS LDRIFT 10MSOP RoHS:是 類(lèi)別:集成電路 (IC) >> Linear - Amplifiers - Instrumentation 系列:iCMOS® 標(biāo)準(zhǔn)包裝:2,500 系列:- 放大器類(lèi)型:通用 電路數(shù):4 輸出類(lèi)型:- 轉(zhuǎn)換速率:0.6 V/µs 增益帶寬積:1MHz -3db帶寬:- 電流 - 輸入偏壓:45nA 電壓 - 輸入偏移:2000µV 電流 - 電源:1.4mA 電流 - 輸出 / 通道:40mA 電壓 - 電源，單路/雙路(±):3 V ~ 32 V，±1.5 V ~ 16 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:14-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:14-TSSOP 包裝:帶卷 (TR) 其它名稱(chēng):LM324ADTBR2G-NDLM324ADTBR2GOSTR
AD8251ARMZ-RL 功能描述:IC AMP INST ICMOS LDRIFT 10MSOP RoHS:是 類(lèi)別:集成電路 (IC) >> Linear - Amplifiers - Instrumentation 系列:iCMOS® 標(biāo)準(zhǔn)包裝:150 系列:- 放大器類(lèi)型:音頻 電路數(shù):2 輸出類(lèi)型:- 轉(zhuǎn)換速率:5 V/µs 增益帶寬積:12MHz -3db帶寬:- 電流 - 輸入偏壓:100nA 電壓 - 輸入偏移:500µV 電流 - 電源:6mA 電流 - 輸出 / 通道:50mA 電壓 - 電源，單路/雙路(±):4 V ~ 32 V，±2 V ~ 16 V 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:8-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:8-TSSOP 包裝:管件
AD8251ARZ 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:12MHz 20V/us G=1,2,4,8 Programmable Gain iCMOS Instrumentation Amplifier
AD8251ARZ-R7 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:12MHz 20V/us G=1,2,4,8 Programmable Gain iCMOS Instrumentation Amplifier
AD8251ARZ-RL 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:12MHz 20V/us G=1,2,4,8 Programmable Gain iCMOS Instrumentation Amplifier
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠(chǎng)商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*