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參數(shù)資料
| 型號(hào)： | DS17485SN-5+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 18/31頁 |
| 文件大小： | 0K |
| 描述： | IC RTC 5V 4K NV RAM 24-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 31 |
| 類型： | 時(shí)鐘/日歷 |
| 特點(diǎn)： | 警報(bào)器，夏令時(shí)，閏年，NVSRAM，方波輸出 |
| 存儲(chǔ)容量： | 4KB |
| 時(shí)間格式： | HH:MM:SS（12/24 小時(shí)） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | 并聯(lián) |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 電壓 - 電源，電池： | 2.5 V ~ 3.7 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-SOIC W |
| 包裝： | 管件 |
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Bit 7: Valid RAM and Time 2 (VRT2). This status bit
gives the condition of the auxiliary battery. It is set to
logic 1 condition when the external lithium battery is
connected to the VBAUX. If this bit is read as logic 0,
the external battery should be replaced.
Bit 6: Increment in Progress Status (INCR). This bit is
set to 1 when an increment to the time/date registers is
in progress and the alarm checks are being made.
INCR is set to 1 at 122s before the update cycle starts
and is cleared to 0 at the end of each update cycle.
Bit 5: Burst Mode Enable (BME). The burst mode
enable bit allows the extended user RAM address reg-
isters to automatically increment for consecutive reads
and writes. When BME is set to logic 1, the automatic
incrementing is enabled and when BME is set to a logic
0, the automatic incrementing is disabled.
Bit 3: Power Active-Bar Control (PAB). When this bit
is 0, the PWR pin is in the active low state. When this bit
is 1, the PWR pin is in the high-impedance state. The
user can write this bit to logic 1 or 0. If either WF and
WIE = 1 or KF and KSE = 1, the PAB bit is cleared to 0.
Bit 2: RAM Clear Flag (RF). This bit is set to logic 1
when a high-to-low transition occurs on the RCLR input
if RCE = 1. Writing this bit to logic 0 clears it. This bit
can also be written to logic 1 to force an interrupt con-
dition.
Bit 1: Wake-Up Alarm Flag (WF). This bit is set to 1
when a wake-up alarm condition occurs or when the
user writes it to 1. WF is cleared by writing it to 0.
Bit 0: Kickstart Flag (KF). This bit is set to 1 when a
kickstart condition occurs or when the user writes it to
1. This bit is cleared by writing it to logic 0.
Extended Control Registers
Two extended control registers are provided to supply
control and status information for the extended func-
tions offered by the DS17x85/DS17x87. These are des-
ignated as Extended Control Registers 4A and 4B, and
are located in register bank 1, locations 04AH and
04BH, respectively. The functions of the bits within
these registers are described as follows.
DS17285/DS17287/DS17485/DS17487/DS17885/DS17887
Real-Time Clocks
____________________________________________________________________
25
Figure 7. Burst Mode Timing Waveform
ADDRESS + 1
AS
53H
DATA
PWRWL
PWRWH
DATA
CS
AD0-7
DS OR R/W
ADDRESS + 2
*
Reserved bit. This bit is reserved for future use. It can be read and written, but has no effect on operation.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
VRT2
INCR
BME
*
PAB
RF
WF
KF
Extended Control Register (4Ah)
MSB
LSB
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