參數(shù)資料
型號(hào): DS17485SN-5+
廠商: Maxim Integrated Products
文件頁數(shù): 28/31頁
文件大?。?/td> 0K
描述: IC RTC 5V 4K NV RAM 24-SOIC
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 31
類型: 時(shí)鐘/日歷
特點(diǎn): 警報(bào)器,夏令時(shí),閏年,NVSRAM,方波輸出
存儲(chǔ)容量: 4KB
時(shí)間格式: HH:MM:SS(12/24 小時(shí))
數(shù)據(jù)格式: YY-MM-DD-dd
接口: 并聯(lián)
電源電壓: 4.5 V ~ 5.5 V
電壓 - 電源,電池: 2.5 V ~ 3.7 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 24-SOIC W
包裝: 管件
DS17285/DS17287/DS17485/DS17487/DS17885/DS17887
Real-Time Clocks
6
_____________________________________________________________________
POWER-UP/POWER-DOWN CHARACTERISTICS
(TA = -40°C to +85°C) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Recovery at Power-Up
tREC
(Note 9)
20
150
ms
VCC Fall Time, VPF(MAX) to
VPF(MIN)
tF
300
s
VCC Fall Time, VPF(MAX) to
VPF(MIN)
tR
0s
DATA RETENTION (DS17x87 ONLY)
(TA = +25°C)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Expected Data Retention
tDR
(Note 9)
10
Years
CAPACITANCE
(TA = +25°C) (Note 10)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Capacitance on All Input Pins
Except X1
CIN
(Note 10)
12
pF
Capacitance on IRQ, SQW, and
DQ0–DQ7 Pins
CIO
(Note 10)
12
pF
AC TEST CONDITIONS
PARAMETER
CONDITIONS
Input Pulse Levels:
0 to 3.0V
Output Load Including Scope and Jig:
50pF + 1TTL Gate
Input and Output Timing Measurement Reference Levels:
Input/Output: VIL max and VIH min
Input Pulse Rise and Fall Times:
5ns
Note 1:
RTC modules can be successfully processed through conventional wave-soldering techniques as long as temperature
exposure to the lithium energy source contained within does not exceed +85°C. However, post-solder cleaning with water-
washing techniques is acceptable, provided that ultrasonic vibrations not used to prevent damage to the crystal.
Note 2:
Limits at -40°C are guaranteed by design and not production tested.
Note 3:
All voltages are referenced to ground.
Note 4:
All outputs are open.
Note 5:
Specified with CS = RD = WR = VCC, ALE, AD0–AD7 = 0.
Note 6:
Applies to the AD0–AD7 pins, IRQ, and SQW when each is in a high-impedance state.
Note 7:
Measured with a 32.768kHz crystal attached to X1 and X2.
Note 8:
Measured with a 50pF capacitance load plus 1TTL gate.
Note 9:
If the oscillator is disabled in software, or if the countdown chain is in reset, tREC is bypassed, and the part becomes
immediately accessible.
Note 10: Guaranteed by design. Not production tested.
WARNING: Negative undershoots below -0.3V while the part is in battery-backed mode can cause loss of
data.
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