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參數(shù)資料
| 型號： | AD8306ARZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LOG-LIMITING AMP 16-SOIC |
| 標準包裝： | 1,000 |
| 類型： | 限制-對數(shù)放大器 |
| 應(yīng)用： | 接收器信號強度指示（RSSI） |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SO |
| 包裝： | 帶卷 (TR) |
REV. A
AD8306
–13–
10 mV/dB The AD8031 rail-to-rail op amp, used in both ex-
amples, can swing from 50 mV to 4.95 mV on a single +5 V
supply. If high output current is required (> 10 mA), the AD8051,
which also has rail-to-rail capability but can deliver up to 45 mA
of output current, can be used.
APPLICATIONS
The AD8306 is a versatile and easily applied log-limiting ampli-
fier. Being complete, it can be used with very few external com-
ponents, and most applications can be accommodated using the
simple connections shown in the preceding section. A few ex-
amples of more specialized applications are provided here.
High Output Limiter Loading
The AD8306 can generate a fairly large output power at its
differential limiter output interface. This may be coupled into a
50
grounded load using the narrow-band coupling network
following similar lines to those provided for input matching.
Alternatively, a flux-linked transformer, having a center-tapped
primary, may be used. Even higher output powers can be ob-
tained using emitter-followers. In Figure 31, the supply voltage
to the AD8306 is dropped from 5 V to about 4.2 V, by the
diode. This increases the available swing at each output to about
2 V. Taking both outputs differentially, a square wave output of
4 V p-p can be generated.
1
2
3
4
5
6
7
8
VLOG
VPS2
PADL
LMHI
LMLO
PADL
FLTR
LMDR
COM2
VPS1
PADL
INHI
INLO
PADL
COM1
ENBL
AD8306
9
10
11
14
15
16
0.1 F
10
RLIM
RSSI
3V TO 5V
0.1 F
10
12
13
+5V
IN914
APPROX. 4.2V
RLOAD
SET RL = 5*RLIM
5V TO 3V
DIFFERENTIAL
OUTPUT = 4V pk-pk
RLOAD
Figure 31. Increasing Limiter Output Voltage
When operating at high output power levels and high frequen-
cies, very careful attention must be paid to the issue of stability.
Oscillation is likely to be observed when the input signal level is
low, due to the extremely high gain-bandwidth product of the
AD8306 under such conditions. These oscillations will be less
evident when signal-balancing networks are used, operating at
frequencies below 200 MHz, and they will generally be fully
quenched by the signal at input levels of a few dB above the
noise floor.
Modulated Limiter Output
The limiter output stage of the AD8306 also provides an analog
multiplication capability: the amplitude of the output square
wave can be controlled by the current withdrawn from LMDR
(Pin 9). An analog control input of 0 V to +1 V is used to gener-
ate an exactly-proportional current of 0 mA to 10 mA in the npn
transistor, whose collector is held at a fixed voltage of
400 mV
by the internal bias in the AD8306. When the input signal is
above the limiting threshold, the output will then be a square-
wave whose amplitude is proportional to the control bias.
1
2
3
4
5
6
7
8
VLOG
VPS2
PADL
LMHI
LMLO
PADL
FLTR
LMDR
COM2
VPS1
PADL
INHI
INLO
PADL
COM1
ENBL
AD8306
9
10
11
14
15
16
10
12
13
VS
1.8k
AD8031
0.1 F
RSSI
0.1 F
VARIABLE
OUTPUT
8.2k
0V TO +1V
18
0mA TO
10mA
2N3904
0.1 F
Figure 32. Variable Limiter Output Programming
Effect of Waveform Type on Intercept
The AD8306 fundamentally responds to voltage and not to
power. A direct consequence of this characteristic is that input
signals of equal rms power, but differing crest factors, will pro-
duce different results at the log amp’s output.
The effect of differing signal waveforms is to shift the effective
value of the log amp’s intercept. Graphically, this looks like a
vertical shift in the log amp’s transfer function. The device’s
logarithmic slope however is not affected. For example, consider
the case of the AD8306 being alternately fed by an unmodu-
lated sine wave and by a single CDMA channel of the same rms
power. The AD8306’s output voltage will differ by the equiva-
lent of 3.55 dB (71 mV) over the complete dynamic range of the
device (the output for a CDMA input being lower).
Table II shows the correction factors that should be applied to
measure the rms signal strength of a various signal types. A sine
wave input is used as a reference. To measure the rms power of
a square wave, for example, the mV equivalent of the dB value
given in the table (20 mV/dB times 3.01 dB) should be sub-
tracted from the output voltage of the AD8306.
Table II. Shift in AD8306 Output for Signals with Differing
Crest Factors
Correction Factor
Signal Type
(Add to Output Reading)
Sine Wave
0 dB
Square Wave or DC
–3.01 dB
Triangular Wave
+0.9 dB
GSM Channel (All Time Slots On)
+0.55 dB
CDMA Channel (Forward Link, 9
Channels On)
+3.55 dB
CDMA Channel (Reverse Link)
+0.5 dB
PDC Channel (All Time Slots On) +0.58 dB
Gaussian Noise
+2.51 dB
Evaluation Board
An evaluation board, carefully laid out and tested to demon-
strate the specified high speed performance of the AD8306 is
available. Figure 33 shows the schematic of the evaluation
board, which fairly closely follows the basic connections sche-
matic shown in Figure 27. For ordering information, please
refer to the Ordering Guide. Links, switches and component
settings for different setups are described in Table III.
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| AD8306-EVAL | 制造商:Analog Devices 功能描述:Evaluation Kit For 5 MHz-400 MHz 100 DB High Precision Limiting-Logarithmic Amplifier 制造商:Analog Devices 功能描述:AD8306 EVALUATION BOARD - Bulk |
| AD8306-EVALZ | 制造商:Analog Devices 功能描述:Evaluation Board For AD8306 制造商:Analog Devices 功能描述:EVALUATION BOARDS - Bulk 制造商:Analog Devices 功能描述:IC LOGARITHMIC AMPLIFIER ((NS)) |
| AD8307 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Cost DC-500 MHz, 92 dB Logarithmic Amplifier |
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| AD8307AN | 功能描述:IC LOGARITHMIC AMP 8-DIP RoHS:否 類別:集成電路 (IC) >> 線性 - 放大器 - 專用 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:60 系列:- 類型:可變增益放大器 應(yīng)用:CATV 安裝類型:表面貼裝 封裝/外殼:20-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:20-TQFN-EP（5x5） 包裝:托盤 |
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