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| 型號(hào)： | AD8306ARZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 14/16頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC LOG-LIMITING AMP 16-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Choosing and Using RF Detectors |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 限制-對(duì)數(shù)放大器 |
| 應(yīng)用： | 接收器信號(hào)強(qiáng)度指示（RSSI） |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SO |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁(yè)面： | 550 (CN2011-ZH PDF) |
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REV. A
AD8306
–7–
PRODUCT OVERVIEW
The AD8306 is built on an advanced dielectrically-isolated
complementary bipolar process using thin-film resistor technol-
ogy for accurate scaling. It follows well-developed foundations
proven over a period of some fifteen years, with constant refine-
ment. The backbone of the AD8306 (Figure 19) comprises a
chain of six main amplifier/limiter stages, each having a gain of
12.04 dB (
×4) and small-signal –3 dB bandwidth of 850 MHz.
The input interface at INHI and INLO (Pins 4 and 5) is fully
differential. Thus it may be driven from either single-sided or
balanced inputs, the latter being required at the very top end of
the dynamic range, where the total differential drive may be as
large as 4 V in amplitude.
The first six stages, also used in developing the logarithmic
RSSI output, are followed by a versatile programmable-output,
and thus programmable-gain, final limiter section. Its open-
collector outputs are also fully differential, at LMHI and LMLO
(Pins 12 and 13). This output stage provides a gain of 18 dB
when using equal valued load and bias setting resistors and the
pin-to-pin output is used. The overall voltage gain is thus 90 dB.
When using RLIM = RLOAD = 200 , the additional current
consumption in the limiter is approximately 2.8 mA, of which
2 mA goes to the load. The ratio depends on RLIM (for example,
when 20
, the efficiency is 90%), and the voltage at the pin
LMDR is rather more than 400 mV, but the total load current
is accurately (400 mV)/RLIM.
The rise and fall times of the hard-limited (essentially square-
wave) voltage at the outputs are typically 0.6 ns, when driven by
a sine wave input having an amplitude of 316
V or greater, and
RLOAD = 50 . The change in time-delay (“phase skew”) over
the input range –73 dBV (316
V in amplitude, or –60 dBm in
50
) to –3 dBV (1 V or +10 dBm) is ±56 ps (±2° at 100 MHz).
12dB
LIM
DET
12dB
DET
4
DET
LADR ATTEN
INHI
INLO
I–V
BIAS
CTRL
TEN DETECTORS SPACED 12dB
INTERCEPT
TEMP COMP
BAND-GAP
REFERENCE
ENBL
GAIN
BIAS
LMHI
LMLO
LMDR
VLOG
FLTR
SIX STAGES TOTAL GAIN 72dB
TYP GAIN 18dB
SLOPE
BIAS
12dB
Figure 19. Main Features of the AD8306
The six main cells and their associated full-wave detectors,
having a transconductance (gm) form, handle the lower part of
the dynamic range. Biasing for these cells is provided by two
references, one of which determines their gain, the other being a
band-gap cell which determines the logarithmic slope, and sta-
bilizes it against supply and temperature variations. A special
dc-offset-sensing cell (not shown in Figure 19) is placed at the
end of this main section, and used to null any residual offset at
the input, ensuring accurate response down to the noise floor.
The first amplifier stage provides a short-circuited voltage-noise
spectral-density of 1.07 nV/
√Hz.
The last detector stage includes a modification to temperature-
stabilize the log-intercept, which is accurately positioned so as
to make optimal use of the full output voltage range. Four fur-
ther “top end” detectors are placed at 12.04 dB taps along a
passive attenuator, to handle the upper part of the range. The
differential current-mode outputs of all ten detectors stages are
summed with equal weightings and converted to a single-sided
voltage by the output stage, generating the logarithmic (or RSSI)
output at VLOG (Pin 16), nominally scaled 20 mV/dB (that is,
400 mV per decade). The junction between the lower and upper
regions is seamless, and the logarithmic law-conformance is
typically well within
±0.4 dB over the 80 dB range from –80 dBV
to 0 dBV (–67 dBm to +13 dBm).
The full-scale rise time of the RSSI output stage, which operates
as a two-pole low-pass filter with a corner frequency of 3.5 MHz,
is about 200 ns. A capacitor connected between FLTR (Pin 10)
and VLOG can be used to lower the corner frequency (see be-
low). The output has a minimum level of about 0.34 V (corre-
sponding to a noise power of –78 dBm, or 17 dB above the
nominal intercept of –95 dBm). This rather high baseline level
ensures that the pulse response remains unimpaired at very low
inputs.
The maximum RSSI output depends on the supply voltage and
the load. An output of 2.34 V, that is, 20 mV/dB
× (9 + 108) dB, is
guaranteed when using a supply voltage of 4.5 V or greater and
a load resistance of 50
or higher, for a differential input of
9 dBV (a 4 V sine amplitude, using balanced drives). When
using a 3 V supply, the maximum differential input may still be
as high as –3 dBV (1 V sine amplitude), and the corresponding
RSSI output of 2.1 V, that is, 20 mV/dB
× (–3 + 108) dB is also
guaranteed.
A fully-programmable output interface is provided for the hard-
limited signal, permitting the user to establish the optimal output
current from its differential current-mode output. Its magnitude
is determined by the resistor RLIM placed between LMDR (Pin
9) and ground, across which a nominal bias voltage of ~400 mV
appears. Using RLIM = 200 , this dc bias current, which is
commutated alternately to the output pins, LMHI and LMLO,
by the signal, is 2 mA. (The total supply current is somewhat
higher).
These currents may readily be converted to voltage form by the
inclusion of load resistors, which will typically range from a few
tens of ohms at 400 MHz to as high as 2 k
in lower frequency
applications. Alternatively, a resonant load may be used to extract
the fundamental signal and modulation sidebands, minimizing
the out-of-band noise. A transformer or impedance matching
network may also be used at this output. The peak voltage swing
down from the supply voltage may be 1.2 V, before the output
transistors go into saturation. (The Applications section provides
further information on the use of this interface).
The supply current for all sections except the limiter output
stage, and with no load attached to the RSSI output, is nomi-
nally 16 mA at TA = 27°C, substantially independent of supply
voltage. It varies in direct proportion to the absolute tempera-
ture (PTAT). The RSSI load current is simply the voltage at
VLOG divided by the load resistance (e.g., 2.4 mA max in a
1 k
load). The limiter supply current is 1.1 times that flowing
in RLIM. The AD8306 may be enabled/disabled by a CMOS-
compatible level at ENBL (Pin 8).
In the following simplified interface diagrams, the components
denoted with an uppercase “R” are thin-film resistors having a
very low temperature-coefficient of resistance and high linearity
under large-signal conditions. Their absolute value is typically
within
±20%. Capacitors denoted using an uppercase “C” have
a typical tolerance of
±15% and essentially zero temperature or
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD8306ARZ | 制造商:Analog Devices 功能描述:Logarithmic Amplifier IC |
| AD8306ARZ-REEL | 制造商:Analog Devices 功能描述:SP Amp LOG Amp Single 6.5V 16-Pin SOIC N T/R 制造商:Analog Devices 功能描述:SP AMP LOG AMP SGL 6.5V 16SOIC N - Tape and Reel |
| AD8306ARZ-RL7 | 功能描述:IC LOG-LIMITING AMP 16-SOIC RoHS:是 類別:集成電路 (IC) >> 線性 - 放大器 - 專用 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:60 系列:- 類型:可變?cè)鲆娣糯笃?應(yīng)用:CATV 安裝類型:表面貼裝 封裝/外殼:20-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:20-TQFN-EP（5x5） 包裝:托盤 |
| AD8306-EVAL | 制造商:Analog Devices 功能描述:Evaluation Kit For 5 MHz-400 MHz 100 DB High Precision Limiting-Logarithmic Amplifier 制造商:Analog Devices 功能描述:AD8306 EVALUATION BOARD - Bulk |
| AD8306-EVALZ | 制造商:Analog Devices 功能描述:Evaluation Board For AD8306 制造商:Analog Devices 功能描述:EVALUATION BOARDS - Bulk 制造商:Analog Devices 功能描述:IC LOGARITHMIC AMPLIFIER ((NS)) |
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