參數(shù)資料
型號: AD8307ARZ-RL7
廠商: Analog Devices Inc
文件頁數(shù): 8/24頁
文件大?。?/td> 0K
描述: IC AMP LOGARITHMIC 8-SOIC
標(biāo)準(zhǔn)包裝: 1
類型: 對數(shù)放大器
應(yīng)用: 接收器信號強度指示(RSSI)
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SO
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: AD8307ARZ-RL7DKR
AD8307
Rev. D | Page 16 of 24
It can be desirable to increase the speed of the output response,
with the penalty of increased ripple. One way to do this is by
connecting a shunt load resistor from Pin OUT to ground,
which raises the low-pass corner frequency. This also alters the
logarithmic slope, for example, to 7.5 mV/dB using a 5.36 kΩ
resistor, while reducing the 10% to 90% rise time to 25 ns. The
ripple amplitude for the 50 MHz input remains at 0.5 mV, but
this is now equivalent to ±0.07 dB. If a negative supply is available,
the output pin can be connected directly to the summing node
of an external op amp connected as an inverting mode transresis-
tance stage.
Note that while the AD8307 can operate down to supply voltages
of 2.7 V, the output voltage limit is reduced when the supply
drops below 4 V. This characteristic is the result of necessary
headroom requirements, approximately two VBE drops, in the
design of the output stage.
1.25k
25mV/dB
OUT
2A/dB
0A TO 220A
INT
FROM ALL
DETECTORS
CFLT
C2
1pF
VPS
BIAS
1.25k
~400mV
8.25k
60k
60A
COM
R1
12.5k
C1
2.5pF
3pF
LGP
LGM
1.25k
01
08
2-
03
1
4
7
5
2
Figure 31. Simplified Output Interface
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