VOUT (V) at mV/dB dBV k" />
參數(shù)資料
型號(hào)： AD8309ARUZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 9/20頁(yè)
文件大?。?/td> 0K
描述： IC LOGARITHM AMP 100DB 16-TSSOP
產(chǎn)品培訓(xùn)模塊： Choosing and Using RF Detectors
標(biāo)準(zhǔn)包裝： 1
類(lèi)型： 對(duì)數(shù)放大器
應(yīng)用： 接收器信號(hào)強(qiáng)度指示（RSSI）
安裝類(lèi)型： 表面貼裝
封裝/外殼： 16-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 16-TSSOP
包裝： 管件
產(chǎn)品目錄頁(yè)面： 550 (CN2011-ZH PDF)
REV. B
AD8309
–17–
Table II.
Slope
Intercept R1
R2
R4
R5
VOUT (V) at
mV/dB dBV
k
–88 dBV +12 dBV
40
–102
3.92 8.87 O/C 1
0.56
4.56
50
–103
1.05 9.53 O/C 1
0.75
5.75
40
–90
3.92 8.87 20.5 1.05
0.08
4.08
50
–90
1.05 9.53 15.4 1.07
0.1
5.10
Setting the Limiter Output Level
The limiter output is a pair of differential currents of magni-
tude, IOUT, from high impedance (open-collector) sources.
These are converted to equal-amplitude voltages by supply-
referenced load resistors, RLOAD. The limiter output current is
set by RLIM, the resistor connected between Pin 9 (LMDR) and
ground depending on the application, the resulting voltage may
be used in a fully balanced or unbalanced manner. It is good
practice to retain the both resistors, whichever output mode is
used. The unbalanced, or single sided mode, is more inclined to
result in instabilities caused by the very high gain of the signal
path. If the limiter output is not needed, LMDR should be left
open with LMHI and LMLO being tied to VPS2.
The limiter output current is set by the equation:
IOUT = –400 mV/RLIM
and has an absolute accuracy of
±5%.
The voltage on each of the limiter pins will be given by:
VLIM = VS – 400 mV × RLOAD/RLIM
The limiter current may be set as high as 10 mA, which requires
RLIM to be 40 ohms, and can be optionally increased somewhat
beyond this level. It is inadvisable, however, to use high bias
currents, since the gain of this wide bandwidth signal path is
proportional to it, and the risk of instability is elevated as RLIM is
reduced (recommended value is 400
).
The limiter output is specified for input levels between –78 dBV
and +9 dBV. The output of the limiter will be unstable for levels
below –78 dBV (–65 dBm).
High Output Limiter Loading
The AD8309 can generate a fairly large output power at its
differential limiter output interface. This may be coupled into a
50
grounded load using the narrow-band coupling network
following similar lines to those provided for input matching.
Alternatively, a flux-linked transformer, having a center-tapped
primary, may be used. Even higher output powers can be ob-
tained using emitter-followers. In Figure 38, the supply voltage
to the AD8309 is dropped from 5 V to about 4.2 V, by the
diode. This increases the available swing at each output to about
2 V. Taking both outputs differentially, a square wave output of
4 V p-p can be generated.
1
2
3
4
5
6
7
8
VLOG
VPS2
PADL
LMHI
LMLO
PADL
FLTR
LMDR
COM2
VPS1
PADL
INHI
INLO
PADL
COM1
ENBL
AD8309
9
10
11
14
15
16
0.1 F
10
RLIM
RSSI
3V TO 5V
0.1 F
10
12
13
+5V
IN914
APPROX. 4.2V
RLOAD
SET RL = 5*RLIM
5V TO 3V
DIFFERENTIAL
OUTPUT = 4V pk-pk
RLOAD
Figure 38. Increasing Limiter Output Voltage
When operating at high output power levels and high frequen-
cies, very careful attention must be paid to the issue of stability.
Oscillation is likely to be observed when the input signal level is
low, due to the extremely high gain-bandwidth product of the
AD8309 under such conditions. These oscillations will be less
evident when signal-balancing networks are used, operating at
frequencies below 200 MHz, and they will generally be fully
quenched by the signal at input levels of a few dB above the
noise floor.
1
2
3
4
5
6
7
8
VLOG
VPS2
PADL
LMHI
LMLO
PADL
FLTR
LMDR
COM2
VPS1
PADL
INHI
INLO
PADL
COM1
ENBL
AD8309
9
10
11
14
15
16
10
12
13
VS
0.1 F
VR2
10k
INT
INPUT
R1
R2
VR1
2k
SLOPE
R3
33.2k
R5
R4
R6
1.96k
AD8031
GND
RSSI
AD8309 SUPPLY DROPPED TO 3V
RD = (VS –3V)/25mA
0.1 F
Figure 37. Buffered RSSI Output with Slope and Intercept Adjustments
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