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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | AD8328ARQZ |
| 寤犲晢锛� | Analog Devices Inc |
| 鏂囦欢闋佹暩(sh霉)锛� | 3/20闋� |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | IC LINE DRIVE CABLE 5V 20-QSOP |
| 鐢�(ch菐n)鍝佽畩鍖栭€氬憡锛� | AD8328 Discontinuation 02/Mar/2012 |
| 妯欐簴鍖呰锛� | 56 |
| 椤炲瀷锛� | 绶氳矾椹�(q奴)鍕曞櫒锛岀櫦(f膩)灏勫櫒 |
| 鎳�(y墨ng)鐢細 | 瑾�(di脿o)鍒惰В瑾�(di脿o)鍣�锛屾闋傜洅 |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 20-SSOP锛�0.154"锛�3.90mm 瀵級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 20-QSOP |
| 鍖呰锛� | 绠′欢 |
| 鐢�(ch菐n)鍝佺洰閷勯爜闈細 | 765 (CN2011-ZH PDF) |
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AD8328
Rev. A | Page 11 of 20
DATEN
SDATA
CLK
VCC
SLEEP
NC
GND
VCC
VIN鈥�
VIN+
BYP
AD8328
QSOP
TXEN
VCC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
SLEEP
GND
TXEN
RAMP
VOUT鈥�
VOUT+
GND
TOKO 458PT-1087
1k
DATEN
SDATA
CLK
VIN+
VIN鈥�
165
0.1渭F
10F
0.1F
03
15
8-
0
20
TO DIPLEXER
ZIN = 75
ZIN = 150
Figure 20. Typical Application Circuit
Table 6. Adjacent Channel Power
Adjacent Channel Symbol Rate (kSym/s)
Channel Symbol Rate (kSym/s)
160
320
640
1280
2560
5120
160
58
60
63
66
64
320
58
59
60
64
66
65
640
60
58
59
61
64
65
1280
62
60
59
60
61
63
2560
64
62
60
59
60
61
5120
66
65
62
61
59
60
The output impedance of the AD8328 is 300 惟, regardless
of whether the amplifier is in transmit enable or transmit
disable mode. This, when combined with a 2:1 voltage ratio
(4:1 impedance ratio) transformer, eliminates the need for
external back termination resistors. If the output signal is being
evaluated using standard 50 惟 test equipment, a minimum loss
75 惟 to 50 惟 pad must be used to provide the test circuit with
the proper impedance match. The AD8328 evaluation board
provides a convenient means to implement a matching attenuator.
Soldering a 43.3 惟 resistor in the R15 placeholder and an 86.6 惟
resistor in the R16 placeholder allows testing on a 50 惟 system.
When using a matching attenuator, it should be noted that there
is a 5.7 dB of power loss (7.5 dB voltage) through the network.
POWER SUPPLY
The 5 V supply should be delivered to each of the VCC pins via a
low impedance power bus to ensure that each pin is at the same
potential. The power bus should be decoupled to ground using
a 10 渭F tantalum capacitor located close to the AD8328. In
addition to the 10 渭F capacitor, each VCC pin should be individually
decoupled to ground with ceramic chip capacitors located close
to the pins. The bypass pin, BYP, should also be decoupled. The
PCB should have a low impedance ground plane covering all
unused portions of the board, except in areas of the board
where input and output traces are in close proximity to the
AD8328 and the output transformer. All AD8328 ground pins
must be connected to the ground plane to ensure proper
grounding of all internal nodes.
SIGNAL INTEGRITY LAYOUT CONSIDERATIONS
Careful attention to printed circuit board layout details will
prevent problems due to board parasitics. Proper RF design
techniques are mandatory. The differential input and output
traces should be kept as short as possible. Keeping the traces
short minimizes parasitic capacitance and inductance. This is
most critical between the outputs of the AD8328 and the 2:1
output transformer. It is also critical that all differential signal
paths be symmetrical in length and width. In addition, the
input and output traces should be adequately spaced to
minimize coupling (crosstalk) through the board. Following
these guidelines optimizes the overall performance of the
AD8328 in all applications.
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| AD8328ARQZ-REEL | 鍒堕€犲晢:Analog Devices 鍔熻兘鎻忚堪:SP Amp Line Driver Amp Single 5.25V 20-Pin QSOP T/R 鍒堕€犲晢:Rochester Electronics LLC 鍔熻兘鎻忚堪:QSOP LOW COST +5V CABLE LINE DRIVER - Tape and Reel 鍒堕€犲晢:Analog Devices 鍔熻兘鎻忚堪:IC,Digitally Controlled Gain Amplifier,SINGLE,SSOP,20PIN,PLASTIC |
| AD8330 | 鍒堕€犲晢:AD 鍒堕€犲晢鍏ㄧū:Analog Devices 鍔熻兘鎻忚堪:Low Cost, DC to 150 MHz Variable Gain Amplifier |
| AD8330_06 | 鍒堕€犲晢:AD 鍒堕€犲晢鍏ㄧū:Analog Devices 鍔熻兘鎻忚堪:Low Cost DC to 150 MHz Variable Gain Amplifier |
| AD8330_08 | 鍒堕€犲晢:AD 鍒堕€犲晢鍏ㄧū:Analog Devices 鍔熻兘鎻忚堪:Low Cost, DC to 150 MHz Variable Gain Amplifier |
| AD8330ACP | 鍒堕€犲晢:AD 鍒堕€犲晢鍏ㄧū:Analog Devices 鍔熻兘鎻忚堪:Low Cost DC-150 MHz Variable Gain Amplifier |
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