參數(shù)資料
型號(hào): AD8369ARUZ
廠商: Analog Devices Inc
文件頁數(shù): 21/24頁
文件大?。?/td> 0K
描述: IC AMP VGA 16TSSOP
標(biāo)準(zhǔn)包裝: 96
系列: X-AMP®
放大器類型: 可變?cè)鲆?br>
電路數(shù): 1
轉(zhuǎn)換速率: 1200 V/µs
-3db帶寬: 600MHz
電流 - 輸入偏壓: 160µA
電流 - 電源: 37mA
電壓 - 電源,單路/雙路(±): 3 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 16-TSSOP
包裝: 管件
產(chǎn)品目錄頁面: 775 (CN2011-ZH PDF)
REV. 0
–6–
AD8369
PIN CONFIGURATION
1
2
3
4
5
6
7
8
16
15
12
11
9
10
14
AD8369
INLO
COMM
BIT0
BIT1
BIT2
BIT3
DENB
OPLO
OPHI
CMDC
FILT
SENB
VPOS
PWUP
COMM
INHI
13
TOP VIEW
(Not To Scale)
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Function
1
INLO
Balanced Differential Input. Internally biased, should be ac-coupled.
2
COMM
Device Common. Connect to low impedance ground.
3
BIT0
Gain Selection Least Significant Bit. Used as DATA input signal when in serial mode of operation.
4
BIT1
Gain Selection Control Bit. Used as CLOCK input pin when in serial mode of operation.
5
BIT2
Gain Selection Control Bit. Inactive when in serial mode of operation.
6
BIT3
Gain Selection Most Significant Bit. Inactive when in serial mode of operation.
7
DENB
Data Enable Pin. Writes data to register. See Timing Specifications for details.
8
OPLO
Balanced Differential Output. Biased to midsupply, should be ac-coupled.
9
OPHI
Balanced Differential Output. Biased to midsupply, should be ac-coupled.
10
CMDC
Common-Mode Decoupling Pin. Connect bypass capacitor to ground for additional common-mode supply
decoupling beyond the existing internal decoupling.
11
FILT
High-Pass Filter Connection. Used to set high-pass corner frequency.
12
SENB
Serial or Parallel Interface Select. Connect SENB to VPOS for serial operation. Connect SENB to COMM
for parallel operation.
13
VPOS
Positive Supply Voltage, VS = +3 V to +5.5 V.
14
PWUP
Power-Up Pin. Connect PWUP to VPOS to power up the device. Connect PWUP to COMM to power-down.
15
COMM
Device Common. Connect to a low impedance ground.
16
INHI
Balanced Differential Input. Internally biased, should be ac-coupled.
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