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參數(shù)資料
| 型號： | AD8392AAREZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/12頁 |
| 文件大小： | 0K |
| 描述： | IC LINE DRVR ADSL/ADSL 28-TSSOP |
| 標準包裝： | 2,500 |
| 類型： | 驅動器 |
| 驅動器/接收器數(shù)： | 2/0 |
| 規(guī)程： | xDSL |
| 電源電壓： | 5 V ~ 24 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.173"，4.40mm 寬）裸露焊盤 |
| 供應商設備封裝： | 28-HTSSOP |
| 包裝： | 帶卷 (TR) |
AD8392A
Rev. 0 | Page 4 of 12
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Rating
Supply Voltage
±13 V (+26 V)
Power Dissipation
See Figure 3
Storage Temperature Range
65°C to +150°C
Operating Temperature Range
40°C to +85°C
Lead Temperature (Soldering 10 sec)
300°C
Junction Temperature
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, θJA is specified
for the device soldered in the circuit board for surface-mount
packages.
Table 3.
Package Type
θJA
Unit
LFCSP-32 (CP)
27.27
°C/W
TSSOP-28/EP (RE)
35.33
°C/W
Maximum Power Dissipation
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS). Assuming that the load (RL) is midsupply,
the total drive power is VS/2 × IOUT, some of which is dissipated
in the package and some in the load (VOUT × IOUT).
RMS output voltages should be considered. If RL is referenced
to VS as in single-supply operation, the total power is VS × IOUT.
In single supply with RL to VS, worst case is VOUT = VS/2.
Airflow increases heat dissipation, effectively reducing θJA. In
addition, more metal directly in contact with the package leads
from metal traces, through holes, ground, and power planes
reduces the θJA.
Figure 3 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the LFCSP-32 and
TSSOP-28/EP packages on a JEDEC standard 4-layer board.
θJA values are approximations.
0
1
2
3
4
5
6
7
–40 –30 –20 –10
0
10
20
30
40
50
60
70
80
90
TEMPERATURE (°C)
M
AX
IM
U
M
P
O
W
E
R
DI
S
IP
AT
IO
N
(
W
)
TJ = 150°C
LFCSP-32
TSSOP-28/EP
0
64
77
-00
3
Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
See the Thermal Considerations section for additional thermal
design guidance.
ESD CAUTION
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