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參數(shù)資料
| 型號： | ISL26710IRTZ-T |
| 廠商： | Intersil |
| 文件頁數(shù)： | 9/21頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 10BIT SAR 1MSPS 8-TDFN |
| 標(biāo)準(zhǔn)包裝： | 6,000 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 8.5mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-WDFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 8-TDFN（3x3） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個(gè)差分，單極 |
ISL26712, ISL26710, ISL26708
17
FN7999.3
September 5, 2012
SHORT CYCLING
In cases where a lower resolution conversion is acceptable, CS can
be pulled high before all SCLK falling edges have elapsed. This is
referred to as short cycling, and it can be used to further optimize
power consumption. In this mode a lower resolution result will be
output, but the ADC will enter static mode sooner and exhibit a
lower average power consumption than if the complete conversion
cycle were carried out. The minimum acquisition time (tACQ)
requirement of 200ns must be met for the next conversion to be
valid.
POWER-ON RESET
When power is first applied, the ISL26712/10/08 performs a
power-on reset that requires approximately 2.5ms to execute. After
this is complete, a single dummy conversion must be executed (by
taking CS low) in order to initialize the switched capacitor track and
hold. The dummy conversion cycle will take 1s with an 18MHz
SCLK. Once the dummy cycle is complete, the ADC mode will be
determined by the state of CS. Regular conversions can be started
immediately after this dummy cycle is completed and time has
been allowed for proper acquisition.
ACQUISITION TIME
To achieve the maximum sample rate (1 MSps) in the ISL26712
device, the maximum acquisition time is 200ns. For slower
conversion rates, or for conversions performed using a slower
SCLK value than 18MHz, the minimum acquisition time is 200ns.
This same minimum applies to the ISL26710 and ISL26708. This
minimum acquisition time applies to all the devices if short
cycling is utilized.
POWER vs THROUGHPUT RATE
The ISL26712/10/08 provide reduced power consumption at
lower conversion rates by automatically switching into a
low-power mode after completing a conversion. The average
power consumption of the ADC decreases at lower throughput
rates. Figure 35 shows the typical power consumption over a
wide range of throughput rates.
Serial Digital Interface
Conversion data is accessed with an SPI-compatible serial
interface. The interface consists of the serial clock (SCLK), serial
data output (SDATA), and chip select (CS).
The serial interface is designed around using 16 SCLK cycles to
perform an autozero on the SAR comparator and additional SCLK
cycles for SAR comparator decisions (12 SLCKs in the 12-bit
device, 10 SCLKs in the 10-bit device, and 8 SCLKs in the 8-bit
device). If short cycling is not used, all converter throughput
cycles take 16 SCLKs. The SDATA output goes low after the last
conversion decision has been presented to the SDATA output, as
Data Format
Output data is encoded in two’s complement format as shown in
Table 1. The voltage levels in the table are idealized and don’t
account for any gain/offset errors or noise.
Terminology
Signal-to-(Noise + Distortion) Ratio (SINAD)
This is the measured ratio of signal-to-(noise + distortion) at the
output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the sum of all nonfundamental signals up
to half the sampling frequency (fs/2), excluding DC. The ratio
is dependent on the number of quantization levels in the
digitization process; the more levels, the smaller the quantization
noise. The theoretical signal-to-(noise + distortion) ratio for an
ideal N-bit converter with a sine wave input is given by
Equation 1:
Thus, for a 12-bit converter this is 74dB, and for a 10-bit this is 62dB.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the ISL26712/10/08, it is
defined as Equation 2:
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5, and V6 are the rms amplitudes of the second to the
sixth harmonics.
Peak Harmonic or Spurious Noise (SFDR)
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding DC) to the rms value of the
0.01
0.1
1
10
100
0
50
100
150
200
250
300
350
THROUGHPUT (Ksps)
PO
WER
(mW)
VDD = 3V
VDD = 5V
FIGURE 35. POWER CONSUMPTION vs THROUGHPUT RATE
TABLE 1. OUTPUT CODES - DIFFERENTIAL
Input Voltage
Two’s Complement (12-bit)
>(VFS-1.5 LSB)
7FF
VFS-1.5 LSB
7FF
...
7FE
-0.5 LSB
000
…
FFF
-VFS +0.5 LSB
801
…
800
NOTE: VFS in the table above equals the voltage between AIN+ and AIN-.
Differential full scale is equal to 2* VREF.
Signal-to-(Noise + Distortion)
6.02 N
1.76
+
()dB
=
(EQ. 1)
(EQ. 2)
THD dB
()
20
V
2
V
3
2
V
4
2
V
5
2
V
6
2
++
V
1
2
------------------------------------------------------------------------
log
=
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