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參數(shù)資料
| 型號： | AD8476ACPZ-R7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/24頁 |
| 文件大小： | 0K |
| 描述： | IC AMP DIFF ADC DVR 16LFCSP |
| 標準包裝： | 1,500 |
| 放大器類型： | 差分 |
| 電路數(shù)： | 1 |
| 輸出類型： | 差分，滿擺幅 |
| 轉換速率： | 10 V/µs |
| -3db帶寬： | 5MHz |
| 電流 - 電源： | 330µA |
| 電流 - 輸出 / 通道： | 35mA |
| 電壓 - 電源，單路/雙路(±)： | 3 V ~ 18 V，±1.5 V ~ 9 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-WFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 16-LFCSP-WQ（3x3） |
| 包裝： | 帶卷 (TR) |
AD8476
Data Sheet
Rev. B | Page 20 of 24
LOW POWER ADC DRIVING
The AD8476 is designed to be a low power driver for ADCs
with up to 16-bit precision and sampling rates of up to
250 kSPS. The circuit in Figure 56 shows the AD8476 driving
the AD7687, a 16-bit, 250 kSPS fully differential SAR ADC.
The filter between the AD8476 and the ADC reduces high
frequency noise and reduces switching transients from the
sampling of the ADC.
Choose the values of this filter with care. Optimal values for the
filter may need to be determined empirically, but the guidelines
discussed herein are provided to help the user. For optimum
performance, this filter should be fast enough to settle full-scale
to 0.5 LSB of the ADC within the acquisition time specified in
the ADC data sheet, in this case, the AD7687. If the filter is
slower than the acquisition time, distortion can result that looks
like harmonics. If the filter is too fast, the noise bandwidth of
the amplifier increases, thereby reducing the SNR of your
system.
Additional considerations help determine the values of the
individual components. THD of the ADC is likely to increase
with source resistance. This is stated in the ADC data sheet.
To reduce this effect, try to use smaller resistance and larger
capacitance. Large capacitance values much greater than 2 nF
are hard for the amplifier to drive. Higher capacitance also
increases the effect of changes in output impedance.
It is also important to consider the signal frequency range of
interest. The AD8476 THD decreases with higher frequency
(see Figure 42) and output impedance increases with higher
frequency (see Figure 49). This higher output impedance yields
slower settling, thus be certain to choose your capacitance so
that the filter still meets the settling requirement at the
maximum frequency of interest.
In the application shown, a 100 Ω resistors and 2.2 nF
capacitors at each output were chosen. For driving the AD7687,
this combination yields an SNR loss of 2.5 dB and good THD
performance for a 20 kHz fundamental frequency, with an ADC
throughput rate of 250kSPS. The filter bandwidth can be
determined by the following equation:
RC
Frequency
Filter
2
1
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–180
–170
–160
–150
0
20406080
100
120
140
ADC
F
U
L
S
C
AL
E
(
d
B)
FREQUENCY (kHz)
1
019
5-
064
VIN = 8V p-p
THD = –112dB
SNR = 93dB
Figure 55. FFT of AD8476 Driving the AD7687
10
19
5-
06
3
AD8476
AD7687
–OUT
+OUT
+IN
–IN
VOCM
–VS
+VS
+5V
VDD
IN–
IN+
+2.5V
+1.8V TO +5V
+5V
REF
GND
VIO
SDI
SCK
SDO
CNV
100
2.2nF
+4.5V
+2.5V
+0.5V
4V
+4V
+2V
0V
4V
+4V
+2V
0V
4V
+4.5V
+2.5V
+0.5V
4V
Figure 56. AD8476 Conditioning and Level Shifting a Differential Voltage to Drive Single-Supply ADC
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