參數(shù)資料
型號: AD8522ARZ
廠商: Analog Devices Inc
文件頁數(shù): 3/8頁
文件大?。?/td> 0K
描述: IC DAC 12BIT DUAL 5V 14-SOIC
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
產(chǎn)品變化通告: AD8522 Redesign Change 29/Nov/2010
標(biāo)準(zhǔn)包裝: 1
設(shè)置時間: 16µs
位數(shù): 12
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 單電源
功率耗散(最大): 25mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 14-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 14-SO
包裝: 管件
輸出數(shù)目和類型: 2 電壓,單極
采樣率(每秒): 62.5k
產(chǎn)品目錄頁面: 785 (CN2011-ZH PDF)
AD8522
REV. A
–3–
SERIAL INPUT REGISTER DATA FORMAT
Last
First
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
NC
A
B
Sf/Hd
Table I. Truth Table
Data Word
Ext Pins
Sf/Hd
BA
LDA
LDB
DAC Register
Hardware Load:
LX
X
↓↓
Loads DACA + DACB with Data from SR
LX
X
H
Loads DACA with Data from SR
L
XXH
Loads DACB with Data from SR
L
X
H
No Load
Software Decode Load:
H
L
X
No Load
HH
L
↓↓
Loads DACB with Data from SR, See Note 1 Below
H
L
H
No Load
HL
H
↓↓
Loads DACA with Data from SR, See Note 1 Below
H
L
H
No Load
HH
H
↓↓
Loads DACA + DACB with Data from SR, See 1 Note Below
H
No Load
NOTES
1In software mode LDA and LDB perform the same function. They can be tied together or the unused pin should be tied high.
2External Pins LDA and LDB should always be high when shifting Data into the shift register.
3
↓ symbol denotes negative transition.
200A
1.6 VOLT
SDO
1.6mA
Figure 3. AC Timing SDO Pin Load Circuit
A
B
LD
CS
CLK
SDI
t
CSS
t
LD1
t
LD2
t
CSH
t
CL
t
DS
t
DH
SDI
CLK
LD
RS
t
LDW
t
CLRW
FS
ZS
t
S
±1 LSB
ERROR BAND
t
S
t
LD2
DB11
DB10
Sf/Hd
DB4
DB3
DB2
DB1
DB0
NC
VOUT
t
LDW
t
CH
SDO
t
PD
Figure 2. Timing Diagram
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