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| 型號： | AD8552ARZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OPAMP CHOPPER R-R DUAL 8SOIC |
| 產(chǎn)品培訓模塊： | Op Amp Basics |
| 標準包裝： | 2,500 |
| 放大器類型： | 斷路器（零漂移） |
| 電路數(shù)： | 2 |
| 輸出類型： | 滿擺幅 |
| 轉(zhuǎn)換速率： | 0.4 V/µs |
| 增益帶寬積： | 1.5MHz |
| 電流 - 輸入偏壓： | 10pA |
| 電壓 - 輸入偏移： | 1000µV |
| 電流 - 電源： | 850µA |
| 電流 - 輸出 / 通道： | 30mA |
| 電壓 - 電源，單路/雙路(±)： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SO |
| 包裝： | 帶卷 (TR) |
AD8551/AD8552/AD8554
Data Sheet
Rev. E | Page 16 of 24
HIGH GAIN, CMRR, PSRR
Common-mode and power supply rejection are indications of
the amount of offset voltage an amplifier has as a result of a change
in its input common-mode or power supply voltages. As shown
in the previous section, the autocorrection architecture of the
AD855x allows it to quite effectively minimize offset voltages.
The technique also corrects for offset errors caused by common-
mode voltage swings and power supply variations. This results
in superb CMRR and PSRR figures in excess of 130 dB. Because
the autocorrection occurs continuously, these figures can be
maintained across the entire temperature range of the device,
from 40°C to +125°C.
MAXIMIZING PERFORMANCE THROUGH
PROPER LAYOUT
To achieve the maximum performance of the extremely high
input impedance and low offset voltage of the AD855x, care is
needed in laying out the circuit board. The PC board surface
must remain clean and free of moisture to avoid leakage currents
between adjacent traces. Surface coating of the circuit board
reduces surface moisture and provides a humidity barrier,
reducing parasitic resistance on the board. The use of guard
rings around the amplifier inputs further reduces leakage currents.
Figure 52 shows proper guard ring configuration, and Figure 53
shows the top view of a surface-mount layout. The guard ring
does not need to be a specific width, but it should form a
continuous loop around both inputs. By setting the guard ring
voltage equal to the voltage at the noninverting input, parasitic
capacitance is minimized as well. For further reduction of leakage
currents, components can be mounted to the PC board using
Teflon standoff insulators.
AD8552
VOUT
VIN
01101-
052
Figure 52. Guard Ring Layout and Connections to Reduce
PC Board Leakage Currents
V+
AD8552
V–
R2
R1
R2
VREF
VIN2
GUARD
RING
GUARD
RING
VIN1
01101-
053
Figure 53. Top View of AD8552 SOIC Layout with Guard Rings
Other potential sources of offset error are thermoelectric
voltages on the circuit board. This voltage, also called Seebeck
voltage, occurs at the junction of two dissimilar metals and is
proportional to the temperature of the junction. The most common
metallic junctions on a circuit board are solder-to-board trace
and solder-to-component lead. Figure 54 shows a cross-section
of the thermal voltage error sources. If the temperature of the
PC board at one end of the component (TA1) is different from
the temperature at the other end (TA2), the resulting Seebeck
voltages are not equal, resulting in a thermal voltage error.
This thermocouple error can be reduced by using dummy
components to match the thermoelectric error source. Placing
the dummy component as close as possible to its partner ensures
both Seebeck voltages are equal, thus canceling the thermocouple
error. Maintaining a constant ambient temperature on the circuit
board further reduces this error. The use of a ground plane helps
distribute heat throughout the board and reduces EMI noise
pickup.
SOLDER
+
COMPONENT
LEAD
COPPER
TRACE
VSC1
VTS1
TA1
SURFACE-MOUNT
COMPONENT
PC BOARD
TA2
VSC2
VTS2
IF TA1 ≠ TA2, THEN
VTS1 + VSC1 ≠ VTS2 + VSC2
01101-
054
Figure 54. Mismatch in Seebeck Voltages Causes
Thermoelectric Voltage Error
AD8551/
AD8552/
AD8554
AV = 1 + (RF/R1)
NOTES
1. RS SHOULD BE PLACED IN CLOSE PROXIMITY AND
ALIGNMENT TO R1 TO BALANCE SEEBECK VOLTAGES.
RS = R1
R1
RF
VIN
VOUT
01101-
055
Figure 55. Using Dummy Components to Cancel
Thermoelectric Voltage Errors
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