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參數資料
| 型號： | AD8555ACPZ-R2 |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 11/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC AMP CHOPPER 2MHZ 10MA 16LFCSP |
| 標準包裝： | 1 |
| 系列： | DigiTrim® |
| 放大器類型： | 斷路器（零漂移） |
| 電路數： | 1 |
| 轉換速率： | 1.2 V/µs |
| 增益帶寬積： | 2MHz |
| 電流 - 輸入偏壓： | 16nA |
| 電壓 - 輸入偏移： | 2µV |
| 電流 - 電源： | 2mA |
| 電流 - 輸出 / 通道： | 10mA |
| 電壓 - 電源，單路/雙路(±)： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-VQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 16-LFCSP-VQ |
| 包裝： | 剪切帶 (CT) |
| 其它名稱： | AD8555ACPZ-R2CT |
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AD8555
Rev. A | Page 19 of 28
OPEN WIRE FAULT DETECTION
The inputs to A1 and A2, VNEG and VPOS, each have a com-
parator to detect whether VNEG or VPOS exceeds a threshold
voltage, nominally VDD 1.1 V. If (VNEG > VDD 1.1 V) or
(VPOS > VDD 1.1 V), VOUT is clamped to VSS. The output
current limit circuit is disabled in this mode, but the maximum
sink current is approximately 50 mA when VDD = 5 V. The
inputs to A1 and A2, VNEG and VPOS, are also pulled up to
VDD by currents IP1 and IP2. These are both nominally 18 nA
and matched to within 5 nA. If the inputs to A1 or A2 are acci-
dentally left floating, e.g., an open wire fault, IP1 and IP2 pull
them to VDD, which would cause VOUT to swing to VSS, al-
lowing this fault to be detected. It is not possible to disable IP1
and IP2, nor the clamping of VOUT to VSS, when VNEG or
VPOS approaches VDD.
SHORTED WIRE FAULT DETECTION
The AD8555 provides fault detection, in the case where VPOS,
VNEG, or VCLAMP shorts to VDD and VSS. Figure 50 shows
the voltage regions at VPOS, VNEG, and VCLAMP that trigger
an error condition. When an error condition occurs, the VOUT
pin is shorted to VSS. Table 8 lists the voltage levels shown in
VPOS
VNEG
VSS
VINL
VINH
VDD
VSS
VCLL
VDD
VCLAMP
VSS
VINL
VINH
VDD
ERROR
NORMAL
ERROR
NORMAL
ERROR
NORMAL
04598-0-002
Figure 50. Voltage Regions at VPOS, VNEG, and VCLAMP
That Trigger a Fault Condition
Table 8. Typical VINL, VINH, and VCLL Values (VDD = 5 V)
Voltage
Typical Min
Typical Max
Purpose
VINH
3.9 V
4.2 V
Short to VDD
Fault Detection
VINL
0.195 V
0.55 V
Short to VSS
Fault Detection
VCLL
1 V
1.2 V
Short to VSS
Fault Detection
FLOATING VPOS, VNEG, OR VCLAMP FAULT
DETECTION
A floating fault condition at the VPOS, VNEG, or VCLAMP
pins is detected by using a low current to pull a floating input
into an error voltage range, which is defined in the previous
section. In this way, the VOUT pin is shorted to VSS when a
floating input is detected. Table 9 lists the currents used.
Table 9. Floating Fault Detection at VPOS, VNEG, and
VCLAMP
Pin
Typical Current
Goal of Current
VPOS
16 nA pull-up
Pull VPOS above VINH
VNEG
16 nA pull-up
Pull VNEG above VINH
VCLAMP
0.2 μA pull-down
Pull VCLAMP below VCLL
DEVICE PROGRAMMING
Digital Interface
The digital interface allows the first stage gain, second stage
gain, and output offset to be adjusted and allows desired values
for these parameters to be permanently stored by selectively
blowing polysilicon fuses. To minimize pin count and board
space, a single-wire digital interface is used. The digital input
pin, DIGIN, has hysteresis to minimize the possibility of inad-
vertent triggering with slow signals. It also has a pull-down
current sink to allow it to be left floating when programming is
not being performed. The pull-down ensures inactive status of
the digital input by forcing a dc low voltage on DIGIN.
A short pulse at DIGIN from low to high and back to low again,
e.g., between 50 ns and 10 μs long, loads a 0 into a shift register.
A long pulse at DIGIN, e.g., 50 μs or longer, loads a 1 into the
shift register. The time between pulses should be at least 10 μs.
Assuming VSS = 0 V, voltages at DIGIN between VSS and 0.2 ×
VDD are recognized as a low, and voltages at DIGIN between
0.8 × VDD and VDD are recognized as a high. A timing dia-
gram example showing the waveform for entering code 010011
into the shift register is shown in Figure 51.
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