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參數(shù)資料
| 型號： | AD8582ARZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/8頁 |
| 文件大小： | 0K |
| 描述： | IC DAC DUAL 12BIT 5V 24SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 設(shè)置時間： | 16µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 35mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-SOIC |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 2 電壓，單極 |
| 采樣率（每秒）： | 62.5k |
REV. 0
–4–
AD8582
Table I. Control Logic Truth Table
CS
A
/B
LDA
LDB
RST
MSB
Input Register
DAC Register
L
HHHX
Write to A
Latched
L
HHHHX
Write to B
Latched
LLL
H
X
Write to A
A Transparent
L
H
L
H
X
Write to B
B Transparent
H
X
L
H
X
Latched
A & B Transparent
H
X
^
H
X
Latched
XXXXL
L
Reset to Zero Scale
XXXXL
H
Reset to Midscale
H
XXX^
X
Latch Reset Value
^Denotes positive edge triggered.
OPERATION
The AD8582 is a complete, ready-to-use dual 12-bit digital-to-
analog converter. Only one +5 V power supply is necessary for
operation. It contains two voltage-switched, 12-bit, laser-
trimmed digital-to-analog converters, a curvature-corrected
bandgap reference, rail-to-rail output op amps, input registers,
and DAC registers. The parallel data interface consists of twelve
data bits, DB0–DB11, an address select pin A/B, two load
strobe pins (LDA, LDB) and an active low CS strobe. In addi-
tion an asynchronous RST pin will set all DAC register bits to
zero causing the VOUT to become zero volts, or to midscale for
trimming applications when the MSB pin is programmed to
Logic 1. This function is useful for power on reset or system
failure recovery to a known state.
D/A CONVERTER SECTION
The internal DAC is a 12-bit voltage-mode device with an
output that swings from AGND potential to the 2.5 volt in-
ternal bandgap voltage. It uses a laser trimmed R-2R
ladder which is switched by N channel MOSFETs. The out-
put voltage of the DAC has a constant resistance independent
of digital input code. The DAC output (not available to the
user) is internally connected to the rail-to-rail output op amp.
AMPLIFIER SECTION
The internal DAC’s output is buffered by a low power con-
sumption precision amplifier. This low power amplifier contains
a differential PNP pair input stage which provides low offset
voltage and low noise, as well as the ability to amplify the zero-
scale DAC output voltages. The rail-to-rail amplifier is config-
ured in a gain of 1.6384 (= 4.095 V/2.5 V) in order to set the
4.095 volt full-scale output (1 mV/LSB). See Figure 3 for an
equivalent circuit schematic of the analog section.
The op amp has a 16
s typical settling time to 0.01%. There
are slight differences in settling time for negative slewing signals
versus positive. See the oscilloscope photos in the Typical Per-
formances section of this data sheet.
Figure 3. Equivalent Schematic of Analog Portion
R1
R2
VOUT
RAIL-TO-RAIL
OUTPUT
AMPLIFIER
R
BANDGAP
REFERENCE
VREF
2.5V
2R
R
2R
SPDT
N CH FET
SWITCHES
2R
AV = 4.095/2.5
= 1.638V/V
VOLTAGE SWITCHED 12-BIT
R-2R D/A CONVERTER
BUFFER
2R
OUTPUT SECTION
The rail-to-rail output stage of this amplifier has been designed
to provide precision performance while operating near either
power supply. Figure 4 shows an equivalent output schematic of
the rail-to-rail amplifier with its N channel pull-down FETs that
will pull an output load directly to GND. The output sourcing
current is provided by a P channel pull-up device that can sup-
ply GND terminated loads, especially important at the –5%
supply tolerance value of 4.75 volts.
Figure 4. Equivalent Analog Output Circuit
VDD
VOUT
AGND
N-CH
P-CH
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參數(shù)描述 |
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