(@ VDD = +5.0 V ± 5%, R
參數(shù)資料
型號: AD8582ARZ
廠商: Analog Devices Inc
文件頁數(shù): 2/8頁
文件大?。?/td> 0K
描述: IC DAC 12BIT DUAL 5V 24-SOIC
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標準包裝: 31
設(shè)置時間: 16µs
位數(shù): 12
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 單電源
功率耗散(最大): 35mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 24-SOIC
包裝: 管件
輸出數(shù)目和類型: 2 電壓,單極
采樣率(每秒): 62.5k
產(chǎn)品目錄頁面: 785 (CN2011-ZH PDF)
AD8582–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
REV. 0
–2–
(@ VDD = +5.0 V ± 5%, RL = No Load, –40°C ≤ TA ≤ +85°C, unless otherwise noted)
Parameter
Symbol
Condition
Min
Typ
Max
Units
STATIC PERFORMANCE
Resolution
N
Note 1
12
Bits
Relative Accuracy
INL
–2
±3/4
+2
LSB
Differential Nonlinearity
DNL
Monotonic
–1
±3/4
+1
LSB
Zero-Scale Error
V
ZSE
Data = 000
H
+0.2
+3
mV
Full-Scale Voltage
V
FS
Data = FFF
H,
2
4.079
4.095
4.111
V
Full-Scale Tempco
TCV
FS
Notes 2 and 3
±16
ppm/
°C
MATCHING PERFORMANCE
Linearity Matching Error
V
FSA/B
±1
LSB
REFERENCE OUTPUT
Output Voltage
V
REF
2.484
2.500
2.516
V
Output Source Current
I
REF
Note 4
–5
mA
Line Rejection
LN
REJ
0.08
%/V
Load Regulation
LD
REG
I
REF = 0 mA to 5 mA
0.1
%/mA
ANALOG OUTPUT
Output Current
I
OUT
Data = 800
H
±5mA
Load Regulation at Half Scale
LD
REG
R
L = 402 to ∞, Data = 800H
1
3
LSB
Capacitive Load
C
L
No Oscillation
3
500
pF
DYNAMIC CHARACTERISTICS
3
Crosstalk
C
T
>64
dB
Voltage Output Settling Time
5
t
S
To
±1 LSB of Final Value
16
s
Digital Feedthrough
F
T
Signal Measured at DAC Output, While
35
nV s
Changing Data (LDA = LDB = “1”)
LOGIC INPUTS
Logic Input Low Voltage
V
IL
0.8
V
Logic Input High Voltage
V
IH
2.4
V
Input Leakage Current
I
IL
10
A
Input Capacitance
C
IL
Note 3
10
pF
TIMING SPECIFICATIONS
3, 6
Chip Select Pulse Width
t
CSW
30
ns
DAC Select Setup
t
AS
30
ns
DAC Select Hold
t
AH
0ns
Data Setup
t
DS
30
ns
Data Hold
t
DH
10
ns
Load Setup
t
LS
20
ns
Load Hold
t
LH
10
ns
Load Pulse Width
t
LDW
20
ns
Reset Pulse Width
t
RSW
30
ns
SUPPLY CHARACTERISTICS
Positive Supply Current
I
DD
V
IH = 2.4 V, VIL = 0.8 V
4
7
mA
V
IL = 0 V, VDD = +5 V
1
2
mA
Power Dissipation
7
P
DISS
V
IH = 2.4 V, VIL = 0.8 V
20
35
mW
V
IL = 0 V, VDD = +5 V
5
10
mW
Power Supply Sensitivity
PSS
V
DD = ± 5%
0.002
0.004
%/%
NOTES
11 LSB = 1 mV for 0 V to +4.095 V output range.
2Includes internal voltage reference error.
3These parameters are guaranteed by design and not subject to production testing.
4Very little sink current is available at the V
REF pin. Use external buffer if setting up a virtual ground.
5Settling time is not guaranteed for the first six codes 0 through 5.
6All input control signals are specified with t
R = tF
= 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
7Power dissipation is a calculated value I
DD × 5 V.
Specifications subject to change without notice.
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