參數(shù)資料
型號(hào): AD8606AR-REEL
廠商: Analog Devices Inc
文件頁數(shù): 13/24頁
文件大?。?/td> 0K
描述: IC OPAMP GP R-R CMOS 10MHZ 8SOIC
標(biāo)準(zhǔn)包裝: 2,500
系列: DigiTrim®
放大器類型: 通用
電路數(shù): 2
輸出類型: 滿擺幅
轉(zhuǎn)換速率: 5 V/µs
增益帶寬積: 10MHz
電流 - 輸入偏壓: 0.2pA
電壓 - 輸入偏移: 80µV
電流 - 電源: 1mA
電流 - 輸出 / 通道: 80mA
電壓 - 電源,單路/雙路(±): 2.7 V ~ 5.5 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SO
包裝: 帶卷 (TR)
AD8605/AD8606/AD8608
Data Sheet
Rev. N | Page 20 of 24
INSTRUMENTATION AMPLIFIERS
The low offset voltage and low noise of the AD8605 make it an
ideal amplifier for instrumentation applications.
Difference amplifiers are widely used in high accuracy circuits
to improve the common-mode rejection ratio. Figure 54 shows
a simple difference amplifier. Figure 55 shows the common-
mode rejection for a unity gain configuration and for a gain of 10.
Making (R4/R3) = (R2/R1) and choosing 0.01% tolerance yields
a CMRR of 74 dB and minimizes the gain error at the output.
AD8605
5V
V2
V1
R1
1k
R3
1k
R2
10k
R4
10k
VOUT
R4
R3
R2
R1
=
VOUT =
(V2 – V1)
R2
R1
02731-
053
Figure 54. Difference Amplifier, AV = 10
FREQUENCY (Hz)
120
100
0
100
10M
1k
CM
RR
(
d
B)
10k
100k
1M
60
40
20
80
AV = 10
VSY = ±2.5V
AV = 1
02731-
054
Figure 55. Difference Amplifier CMRR vs. Frequency
DAC CONVERSION
The low input bias current and offset voltage of the AD8605
make it an excellent choice for buffering the output of a current
output DAC.
Figure 56 shows a typical implementation of the AD8605 at the
output of a 12-bit DAC.
The DAC8143 output current is converted to a voltage by the
feedback resistor. The equivalent resistance at the output of the
DAC varies with the input code, as does the output capacitance.
R2
AD8605
VOS
RF
CF
R2
V+
V–
02731-
055
R
VREF
Figure 56. Simplified Circuit of the DAC8143 with AD8605 Output Buffer
To optimize the performance of the DAC, insert a capacitor in
the feedback loop of the AD8605 to compensate the amplifier
for the pole introduced by the output capacitance of the DAC.
Typical values for CF range from 10 pF to 30 pF; it can be
adjusted for the best frequency response. The total error at the
output of the op amp can be computed by
+
=
1
Req
R
V
E
F
OS
O
where Req is the equivalent resistance seen at the output of the
DAC. As previously mentioned, Req is code dependent and
varies with the input. A typical value for Req is 15 k.
Choosing a feedback resistor of 10 k yields an error of less
than 200 V.
Figure 57 shows the implementation of a dual-stage buffer
at the output of a DAC. The first stage is used as a buffer.
Capacitor C1 with Req creates a low-pass filter, and thus,
provides phase lead to compensate for frequency response.
The second stage of the AD8606 is used to provide voltage
gain at the output of the buffer.
Grounding the positive input terminals in both stages reduces
errors due to the common-mode output voltage. Choosing R1,
R2, and R3 to match within 0.01% yields a CMRR of 74 dB and
maintains minimum gain error in the circuit.
RFB
VDD
DB11
OUT1
AD7545
AGND
RCS
RP
VIN
15V
VOUT
VREF
1/2
AD8606
1/2
AD8606
C1
33pF
02731-
056
R4
5k
R2
10k
R1
10k
R3
20k
Figure 57. Bipolar Operation
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