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| 型號： | AD8611AR-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC COMP SNGL 4NS ULTRFAST 8-SOIC |
| 標(biāo)準包裝： | 2,500 |
| 類型： | 帶鎖銷 |
| 元件數(shù)： | 1 |
| 輸出類型： | 補充型，TTL |
| 電壓 - 電源，單路/雙路(±)： | 3 V ~ 5 V |
| 電壓 - 輸入偏移（最小值）： | 7mV @ 5V |
| 電流 - 輸入偏壓（最小值）： | 6µA @ 5V |
| 電流 - 靜態(tài)（最大值）： | 10mA，4mA |
| CMRR, PSRR（標(biāo)準）： | 85dB CMRR，73dB PSRR |
| 傳輸延遲（最大）： | 5.5ns |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 安裝類型： | 表面貼裝 |
| 包裝： | 帶卷 (TR) |
AD8611/AD8612
Rev. A | Page 11 of 20
OUTPUT LOADING CONSIDERATIONS
The AD8611 can deliver up to 10 mA of output current without
increasing its propagation delay. The outputs of the device
should not be connected to more than 40 TTL input logic gates
or drive less than 400 Ω of load resistance.
The AD8611 output has a typical output swing between ground
and 1 V below the positive supply voltage. Decreasing the
output load resistance to ground lowers the maximum output
voltage due to the increase in output current. Table 6 shows the
typical output high voltage vs. load resistance to ground.
Table 6. Maximum Output Voltage vs. Resistive Load
Output Load to Ground
V+ VOUT, HI (typ)
300 Ω
1.5 V
500 Ω
1.3 V
1 kΩ
1.2 V
10 kΩ
1.1 V
>20 kΩ
1.0 V
Connecting a 500 Ω to 2 kΩ pull-up resistor to V+ on the
output helps increase the output voltage so that it is closer to the
positive rail; in this configuration, however, the output voltage
will not reach its maximum until 20 ns to 50 ns after the output
voltage switches. This is due to the R-C time constant between
the pull-up resistor and the output and load capacitances. The
output pull-up resistor cannot improve propagation delay.
The AD8611 is stable with all values of capacitive load; however,
loading an output with greater than 30 pF increases the
propagation delay of that channel. Capacitive loads greater than
500 pF also create some ringing on the output wave. Table 7
shows propagation delay vs. several values of load capacitance.
The loading on one output of the AD8611 does not affect the
propagation delay of the other output.
Table 7. Propagation Delay vs. Capacitive Load
CL (pF)
tPD Rising (ns)
tPD Falling (ns)
<10
3.5
33
5
100
8
7
390
14.5
10
680
26
15
USING THE LATCH
TO MAINTAIN A CONSTANT OUTPUT
With the VCC supply at a nominal 5 V, the latch input to the
AD8611/AD8612 can be used to retain data at the output of the
comparator. When the latch voltage goes high, the output
voltage remains in its previous state, independent of changes in
the input voltage.
The setup time for the AD8611/AD8612 is 0.5 ns and the hold
time is 0.5 ns. Setup time is defined as the minimum amount of
time the input voltage must remain in a valid state before the
latch is activated for the latch to function properly. Hold time is
defined as the amount of time the input must remain constant
after the latch voltage goes high for the output to remain latched
to its voltage.
The latch input is TTL and CMOS compatible, so a logic high is
a minimum of 2.0 V and a logic low is a maximum of 0.8 V. The
latch circuitry in the AD8611/AD8612 has no built-in
hysteresis. At or below approximately 4.1 V, the latch pin
becomes unresponsive and should normally be tied low for low
VCC operation.
INPUT STAGE AND BIAS CURRENTS
The AD8611 and AD8612 each use a bipolar PNP differential
input stage. This enables the input common-mode voltage range
to extend from within 2.0 V of the positive supply voltage to
200 mV below the negative supply voltage. Therefore, using a
single 5 V supply, the input common-mode voltage range is
200 mV to +3.0 V. Input common-mode voltage is the average
of the voltages at the two inputs. For proper operation, the input
common-mode voltage should be kept within the common-
mode voltage range.
The input bias current for the AD8611/AD8612 is 4 μA, which
is the amount of current that flows from each input of the
comparator. This bias current goes to zero on an input that is
high and doubles on an input that is low, which is a characteristic
common to any bipolar comparator. Care should be taken in
choosing resistances to be connected around the comparator
because large resistors could significantly decrease the voltage
due to the input bias current.
The input capacitance for the AD8611/AD8612 is typically 3 pF.
This is measured by inserting a 5 kΩ source resistance in series
with the input and measuring the change in propagation delay.
USING HYSTERESIS
Hysteresis can easily be added to a comparator through the
addition of positive feedback. Adding hysteresis to a comparator
offers an advantage in noisy environments where it is undesirable
for the output to toggle between states when the input signal is
close to the switching threshold. Figure 24 shows a simple method
for configuring the AD8611 or AD8612 with hysteresis.
VREF
R1
SIGNAL
COMPARATOR
R2
CF
0
6
010
-02
1
Figure 24. Configuring the AD8611/AD8612 with Hysteresis
In Figure 24, the input signal is connected directly to the
inverting input of the comparator. The output is fed back to the
noninverting input through R1 and R2. The ratio of R1 to
R1 + R2 establishes the width of the hysteresis window, with
VREF setting the center of the window, or the average switching
voltage. The QA or QB output switches low when the input
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| AD8611AR-REEL7 | 功能描述:IC COMP SNGL 4NS ULTRFAST 8-SOIC RoHS:否 類別:集成電路 (IC) >> 線性 - 比較器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準包裝:2,500 系列:- 類型:通用 元件數(shù):1 輸出類型:CMOS，推挽式，滿擺幅，TTL 電壓 - 電源，單路/雙路(±):2.5 V ~ 5.5 V，±1.25 V ~ 2.75 V 電壓 - 輸入偏移（最小值）:5mV @ 5.5V 電流 - 輸入偏壓（最小值）:1pA @ 5.5V 電流 - 輸出（標(biāo)準）:- 電流 - 靜態(tài)（最大值）:24µA CMRR, PSRR（標(biāo)準）:80dB CMRR，80dB PSRR 傳輸延遲（最大）:450ns 磁滯:±3mV 工作溫度:-40°C ~ 85°C 封裝/外殼:6-WFBGA，CSPBGA 安裝類型:表面貼裝 包裝:管件 其它名稱:Q3554586 |
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