參數(shù)資料
型號: AD8671AR
廠商: Analog Devices Inc
文件頁數(shù): 6/20頁
文件大?。?/td> 0K
描述: IC OPAMP GP 10MHZ PREC LN 8SOIC
產品變化通告: Product Discontinuance 27/Oct/2011
標準包裝: 98
放大器類型: 通用
電路數(shù): 1
轉換速率: 4 V/µs
增益帶寬積: 10MHz
電流 - 輸入偏壓: 3nA
電壓 - 輸入偏移: 20µV
電流 - 電源: 3mA
電流 - 輸出 / 通道: 20mA
電壓 - 電源,單路/雙路(±): 10 V ~ 36 V,±5 V ~ 18 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應商設備封裝: 8-SO
包裝: 管件
AD8671/AD8672/AD8674
Data Sheet
Rev. F | Page 14 of 20
AD8671
BAND-PASS FILTER
LOW NOISE OP AMP
MIXER
DEMODULATOR
LOW-PASS FILTER
VGA
ADC
AD10200
AD831
AD8671
AD630
AD8610
AD8369
CODE GENERATOR
03718-B-039
Figure 37. Simplified Block Diagram of a GPS Receiver
GPS RECEIVER
GPS receivers require low noise to minimize RF effects. The
precision of the AD8671 makes it an excellent choice for such
applications. Its very low noise and wide bandwidth make it
suitable for band-pass and low-pass filters without the penalty
of high power consumption.
Figure 37 shows a simplified block diagram of a GPS receiver.
The next section details the design equations.
BAND-PASS FILTER
Filters are useful in many applications; for example, band-pass
filters are used in GPS systems, as discussed in the previous
section. Figure 38 shows a second-order band-pass KRC filter.
18k
10k
2.25k
R3
RB
RA
VCC
VEE
2.25k
R2
2.25k
R1
1nF
C2
VIN
1nF
C2
03718-B-040
Figure 38. Band-Pass KRC Filter
The equal component topology yields a center frequency
RC
fo
π
=
2
and
K
Q
=
4
2
where:
A
B
R
K
+
=1
The band-pass response is shown in Figure 39.
Hz
100k
1k
100
10k
1M
03718-B-041
10M
VS = ±15V
200
V/DIV
Figure 39. Band-Pass Response
PLL SYNTHESIZERS AND LOOP FILTERS
Phase-lock loop filters are used in AM/FM modulation.
Loop filters in PLL design require accuracy and care in their
implementation. The AD8671/AD8672/AD8674 are ideal
candidates for such filter design; the low offset voltage and low
input bias current minimize the output error. In addition to the
excellent dc specifications, the AD8671/AD8672/AD8674 have
a unique performance at high frequencies; the high open-loop
gain and wide bandwidth allow the user to design a filter with a
high closed-loop gain if desirable. To optimize the filter design,
it is recommended to use small value resistors to minimize the
thermal noise. A simple example is shown in Figure 40.
10k
R1
VCC
VEE
1nF
03718-B-042
VCO
C1
CHARGE
PUMP
PHASE
DETECTOR
IN
D
Figure 40. PLL Filter Simplified Block Diagram
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