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參數(shù)資料
| 型號： | AD8801ARZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/16頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 8BIT OCTAL W/SD 16SOIC |
| 產(chǎn)品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 2,500 |
| 系列： | TrimDAC® |
| 設(shè)置時間： | 600ns |
| 位數(shù)： | 8 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 8 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 27.5mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應商設(shè)備封裝： | 16-SOIC |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 8 電壓，單極 |
| 采樣率（每秒）： | 1.7M |
REV. A
–12–
AD8801/AD8803
O1
O2
O3
O4
O5
O6
O7
O8
CS
SHDN
VDD
VREFH
GND
AD8803
+5V
P1.7
P1.6
P1.5
P1.4
1.5
1.6
1.7
PORT 1
8051 C
1.4
SDI
CLK
VREFL
Figure 26. An AD8801/AD8803-8051
C Interface Using
Parallel Port 1
Unlike the serial port interface of Figure 25, the parallel port in-
terface only transmits 11 bits to the AD8801/AD8803. Also, the
BYTESWAP subroutine is not required for the parallel inter-
face, because data can be shifted out MSB first. However, the
results of the two interface methods are exactly identical. In
most cases, the decision on which method to use will be deter-
mined by whether or not the serial data port is available for
communication with the AD8801/AD8803.
An MC68HC11-to-AD8801/AD8803 Interface
Like the 8051, the MC68HC11 includes a dedicated serial data
port (labeled SPI). The SPI port provides an easy interface to
the AD8801/AD8803 (Figure 27). The interface uses three lines
of Port D for the serial data, and one or two lines from Port C
to control the SHDN and RS (AD8801 only) inputs.
SDI
CLK
CS
SHDN
RS (AD8801 ONLY)
AD8801/
AD8803*
MC68HC11
*
MOSI
SCK
SS
PC0
PC1
(PD3)
(PD4)
(PD5)
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 27. An AD8801/AD8803-to-MC68HC11 Interface
A software routine for loading the AD8801/AD8803 from a
68HC11 evaluation board is shown in Listing 3. First, the
MC68HC11 is configured for SPI operation. Bits CPHA and
CPOL define the SPI mode wherein the serial clock (SCK) is
high at the beginning and end of transmission, and data is valid
on the rising edge of SCK. This mode matches the requirements
of the AD8801/AD8803. After the registers are saved on the
stack, the DAC value and address are transferred to RAM and
the AD8801/AD8803’s CS is driven low. Next, the DAC’s ad-
dress byte is transferred to the SPDR register, which automati-
cally initiates the SPI data transfer. The program tests the SPIF
bit and loops until the data transfer is complete. Then the DAC
value is sent to the SPI. When transmission of the second byte is
complete, CS is driven high to load the new data and address
into the AD8801/AD8803.
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