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| 型號： | AD9057BRS-RL40 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 8BIT 40MSPS 20-SSOP T/R |
| 產(chǎn)品變化通告： | Product Discontinuance 27/Oct/2011 |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 位數(shù)： | 8 |
| 采樣率（每秒）： | 40M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 260mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個單端，單極 |
REV. D
AD9057
–7–
THEORY OF OPERATION
The AD9057 combines Analog Devices’ proprietary MagAmp
gray code conversion circuitry with flash converter technology
to provide a high performance, low cost ADC. The design
architecture ensures low power, high speed, and 8-bit accuracy.
A single-ended TTL/CMOS compatible ENCODE input controls
ADC timing for sampling the analog input pin and strobing the
digital outputs (D7–D0). An internal voltage reference (VREF
OUT) may be used to control ADC gain and offset or an exter-
nal reference may be applied.
The analog input signal is buffered at the input of the ADC and
applied to a high speed track-and-hold. The track-and-hold
circuit holds the analog input value during the conversion process
(beginning with the rising edge of the encode command). The
track-and-hold’s output signal passes through the gray code and
flash conversion stages to generate coarse and fine digital
representations of the held analog input level. Decode logic
combines the multistage data and aligns the 8-bit word for
strobed outputs on the rising edge of the encode command. The
MagAmp/Flash architecture of the AD9057 results in three
pipeline delays for the output data.
USING THE AD9057
Analog Inputs
The AD9057 provides a single-ended analog input impedance
of 150 k
W. The input requires a dc bias current of 6 mA (typical)
centered near 2.5 V (
±10%). The dc bias may be provided by
the user or may be derived from the ADC’s internal voltage
reference. Figure 2 shows a low cost dc bias implementation
allowing the user to capacitively couple ac signals directly into
the ADC without additional active circuitry. For best dynamic
performance, the VREF OUT pin should be decoupled to
ground with a 0.1
mF capacitor (to minimize modulation of
the reference voltage) and the bias resistor should be approxi-
mately 1 k
W. A 1 kW bias resistor (±20%) is included within
the AD9057 and may be used to reduce application board size
and complexity.
AD9057
VREF OUT
AIN
0.1 F
5V
VIN
(1V p-p)
VREF IN
BIAS OUT
1k
0.1 F
Figure 2. Capacitively Coupled AD9057
Figure 3 shows typical connections for high performance dc
biasing using the ADC’s internal voltage reference. All compo-
nents may be powered from a single 5 V supply. In the example,
analog input signals are referenced to ground.
AD9057
VREF OUT
VREF IN
AIN
0.1 F
10k
AD8041
5V
1k
5V
1k
VIN
(–0.5V
TO +0.5V)
Figure 3. DC-Coupled AD9057 (Inverted VIN)
Voltage Reference
A stable and accurate 2.5 V voltage reference is built into the
AD9057 (VREF OUT). The reference output may be used to
set the ADC gain/offset by connecting VREF OUT to VREF IN.
The internal reference is capable of providing 300
mA of drive
current (for dc biasing the analog input or other user circuitry).
Some applications may require greater accuracy, improved
temperature performance, or gain adjustments that cannot be
obtained using the internal reference. An external voltage may
be applied to the VREF IN with VREF OUT disconnected for
gain adjustment of up to
±10% (the VREF IN pin is internally
tied directly to the ADC circuitry). ADC gain and offset will
vary simultaneously with external reference adjustment with a
1:1 ratio (a 2% or 50 mV adjustment to the 2.5 V reference
varies ADC gain by 2% and ADC input range center offset by
50 mV). Theoretical input voltage range versus reference input
voltage may be calculated from the following equations:
VRANGE (p-p)
= VREF IN/2.5
VMIDSCALE
= VREF IN
VTOP-OF-RANGE
= VREF IN + VRANGE/2
VBOTTOM-OF-RANGE = VREF IN – VRANGE /2
Digital Logic (5 V/3 V Systems)
The digital inputs and outputs of the AD9057 can easily be
configured to interface directly with 3 V or 5 V logic systems.
The encode and power-down (PWRDN) inputs are CMOS
stages with TTL thresholds of 1.5 V, making the inputs compat-
ible with TTL, 5 V CMOS, and 3 V CMOS logic families. As
with all high speed data converters, the encode signal should be
clean and jitter free to prevent degradation of ADC dynamic
performance.
The AD9057’s digital outputs will also interface directly with
5V or 3 V CMOS logic systems. The voltage supply pin (VDD)
for these CMOS stages is isolated from the analog VD voltage
supply. By varying the voltage on this supply pin, the digital
output high level will change for 5 V or 3 V systems. Optimum
SNR is obtained running the outputs at 3 V. Care should be
taken to isolate the VDD supply voltage from the 5 V analog
supply to minimize digital noise coupling into the ADC.
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| AD9057BRSZ-40 | 功能描述:IC ADC 8BIT 40MSPS 20-SSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):16 采樣率（每秒）:45k 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:315mW 電壓電源:模擬和數(shù)字 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC W 包裝:帶卷 (TR) 輸入數(shù)目和類型:2 個單端，單極 |
| AD9057BRSZ-60 | 功能描述:IC ADC 8BIT 60MSPS 20SSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個單端，單極；2 個差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
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