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參數(shù)資料
| 型號： | AD9059BRS |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 8BIT DUAL 60MSPS 28-SSOP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 8 |
| 采樣率（每秒）： | 60M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 505mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 2 個單端，單極 |
REV. A
AD9059
–7–
THEORY OF OPERATION
The AD9059 combines Analog Devices’ proprietary MagAmp
gray code conversion circuitry with flash converter technology to
provide dual high performance 8-bit ADCs in a single low cost
monolithic device. The design architecture ensures low power,
high speed, and 8-bit accuracy.
The AD9059 provides two linked ADC channels that are clocked
from a single ENCODE input (see Functional Block Diagram).
The two ADC channels simultaneously sample the analog inputs
(AINA and AINB) and provide noninterleaved parallel digital
outputs (D0A–D7A and D0B–D7B). The voltage reference
(VREF) is internally connected to both ADCs so channel gains
and offsets will track if external reference control is desired.
The analog input signal is buffered at the input of each ADC
channel and applied to a high speed track-and-hold. The track-
and-hold circuit holds the analog input value during the
conversion process (beginning with the rising edge of the
ENCODE command). The track-and-hold’s output signal passes
through the gray code and flash conversion stages to generate
coarse and fine digital representations of the held analog input
level. Decode logic combines the multistage data and aligns the
8-bit word for strobed outputs on the rising edge of the ENCODE
command. The MagAmp/Flash architecture of the AD9059
results in three pipeline delays for the output data.
USING THE AD9059
Analog Inputs
The AD9059 provides independent single-ended high impedance
(150 k
) analog inputs for the dual ADCs. Each input requires a
dc bias current of 6
A (typical) centered near 2.5 V (±10%). The
dc bias may be provided by the user or may be derived from the
ADC’s internal voltage reference. Figure 2 shows a low cost dc
bias implementation that allows the user to capacitively couple
ac signals directly into the ADC without additional active cir-
cuitry. For best dynamic performance, the VREF pin should
be decoupled to ground with a 0.1
F capacitor (to minimize
modulation of the reference voltage), and the bias resistor should
be approximately 1 k
.
1
3
1k
AINA
AINB
VREF
AD9059
0.1F
5V
VINA
(1V p-p)
EXTERNAL VREF
(OPTIONAL)
VINB
(1V p-p)
28
Figure 2. Capacity Coupled AD9059
Figure 3 shows typical connections for high performance dc
biasing using the ADC’s internal voltage reference. All compo-
nents may be powered from a single 5 V supply (analog input
signals are referenced to ground).
28
1
10k
1k
AINA
AINB
VREF
AD9059
0.1F
+5V
VINA
VIN B
(–0.5V TO +0.5V)
10k
+5V
5V
AD8041
1k
3
Figure 3. DC-Coupled AD9059 (VIN Inverted)
Voltage Reference
A stable and accurate 2.5 V voltage reference is built into the
AD9059 (VREF). The reference output is used to set the ADC
gain/offset and can provide dc bias for the analog input signals.
The internal reference is tied to the ADC circuitry through an
800
internal impedance and is capable of providing 300 A
external drive current (for dc biasing the analog input or other
user circuitry).
Some applications may require greater accuracy, improved
temperature performance, or gain adjustments that cannot be
obtained using the internal reference. An external voltage may
be applied to the VREF pin to overdrive the internal voltage
reference for gain adjustment of up to
±10% (the VREF pin is
internally tied directly to the ADC circuitry). ADC gain and
offset will vary simultaneously with external reference adjust-
ment with a 1:1 ratio (a 2% or 50 mV adjustment to the 2.5 V
reference varies ADC gain by 2% and ADC offset by 50 mV).
Theoretical input voltage range versus reference input voltage
may be calculated using the following equations.
Vp
p
VREF
V
VREF
V
VREF
V
VREF
V
RANGE
MIDSCALE
TOP OF RANGE
RANGE
BOTTOM OF RANGE
RANGE
()
.
–
=
=+
=
25
2
The external reference should have a 1 mA minimum sink/
source current capability to ensure complete overdrive of the
internal voltage reference.
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| AD9059BRS-REEL | 功能描述:IC ADC 8BIT DUAL 60MSPS 28-SSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
| AD9059BRSZ | 功能描述:IC ADC 8BIT DUAL 60MSPS 28SSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
| AD9059BRSZ-REEL | 功能描述:IC ADC 8BIT DUAL 60MSPS 28SSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個單端，單極；1 個單端，雙極 |
| AD9059PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual 8-Bit, 60 MSPS A/D Converter |
| AD9060 | 制造商:AD 制造商全稱:Analog Devices 功能描述:10-Bit 75 MSPS A/D Converter |
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