DYNAMIC PERFORMANCE (SE)3 Signal-to-Nois" />
參數(shù)資料
型號: AD9201ARS
廠商: Analog Devices Inc
文件頁數(shù): 14/20頁
文件大?。?/td> 0K
描述: IC ADC CMOS 10BIT DUAL 28-SSOP
標(biāo)準(zhǔn)包裝: 47
位數(shù): 10
采樣率(每秒): 20M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 2
功率耗散(最大): 245mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-SSOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 28-SSOP
包裝: 管件
輸入數(shù)目和類型: 4 個單端,單極;2 個差分,單極
–3–
REV. D
AD9201
Parameter
Symbol
Min
Typ
Max
Units
Condition
DYNAMIC PERFORMANCE (SE)3
Signal-to-Noise and Distortion
SINAD
f = 3.58 MHz
52.3
dB
Signal-to-Noise
SNR
f = 3.58 MHz
55.5
dB
Total Harmonic Distortion
THD
f = 3.58 MHz
–55
dB
Spurious Free Dynamic Range
SFDR
f = 3.58 MHz
–58
dB
DIGITAL INPUTS
High Input Voltage
VIH
2.4
V
Low Input Voltage
VIL
0.3
V
DC Leakage Current
IIN
±6
A
Input Capacitance
CIN
2pF
LOGIC OUTPUT (with DVDD = 3 V)
High Level Output Voltage
(IOH = 50
A)
VOH
2.88
V
Low Level Output Voltage
(IOL = 1.5 mA)
VOL
0.095
V
LOGIC OUTPUT (with DVDD = 5 V)
High Level Output Voltage
(IOH = 50
A)
VOH
4.5
V
Low Level Output Voltage
(IOL = 1.5 mA)
VOL
0.4
V
Data Valid Delay
tOD
11
ns
MUX Select Delay
tMD
7ns
Data Enable Delay
tED
13
ns
CL = 20 pF. Output Level to
90% of Final Value
Data High-Z Delay
tDHZ
13
ns
CLOCKING
Clock Pulsewidth High
tCH
22.5
ns
Clock Pulsewidth Low
tCL
22.5
ns
Pipeline Latency
3.0
Cycles
NOTES
1AIN differential 2 V p-p, REFT = 1.5 V, REFB = –0.5 V.
2IMD referred to larger of two input signals.
3SE is single ended input, REFT = 1.5 V, REFB = –0.5 V.
Specifications subject to change without notice.
CLOCK
INPUT
SELECT
INPUT
DATA
OUTPUT
ADC SAMPLE
#1
ADC SAMPLE
#2
ADC SAMPLE
#3
ADC SAMPLE
#4
ADC SAMPLE
#5
Q CHANNEL
OUTPUT ENABLED
I CHANNEL
OUTPUT ENABLED
SAMPLE #1-3
Q CHANNEL
OUTPUT
SAMPLE #1-2
Q CHANNEL
OUTPUT
SAMPLE #1-1
Q CHANNEL
OUTPUT
SAMPLE #1-1
I CHANNEL
OUTPUT
SAMPLE #1
Q CHANNEL
OUTPUT
SAMPLE #1
I CHANNEL
OUTPUT
SAMPLE #2
Q CHANNEL
OUTPUT
tMD
tOD
Figure 1. ADC Timing
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