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參數(shù)資料
| 型號： | AD9203ARUZRL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/28頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT 40MSPS 3V 28-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 40M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 5 |
| 功率耗散（最大）： | 108mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個單端，單極；1 個差分，單極 |
| 其它名稱： | AD9203ARUZRL7-ND AD9203ARUZRL7TR |
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AD9203
Rev. B | Page 14 of 28
00573-025
S2
S3
S1
AD9203
CH
CP
Figure 25. Input Architecture
The structure of the input SHA places certain requirements on
the input drive source. The combination of the pin capacitance,
CP, and the hold capacitance, CH, is typically less than 5 pF. The
input source must be able to charge or discharge this
capacitance to 10-bit accuracy in one half of a clock cycle.
When the SHA goes into track mode, the input source must
charge or discharge capacitor CH from the voltage already stored
on CH to the new voltage. In the worst case, a full-scale voltage
step on the input source must provide the charging current
through the RON (100 ) of Switch 1 and quickly (within 1/2
CLK period) settle. This situation corresponds to driving a low
input impedance. Adding series resistance between the output
of the signal source and the AIN pin reduces the drive
requirements placed on the signal source. Figure 26 shows this
configuration. The bandwidth of the particular application
limits the size of this resistor. To maintain the performance
outlined in the data sheet specifications, the resistor should be
limited to 50 or less. The series input resistor can be used to
isolate the driver from the AD9203’s switched capacitor input.
The external capacitor may be selected to limit the bandwidth
into the AD9203. Two input RC networks should be used to
balance differential input drive schemes (Figure 26).
The input span of the AD9203 is a function of the reference
voltage. For more information regarding the input range, see
Operation sections of the data sheet.
00573-026
AIN
VS
<50
AD9203
Figure 26. Simple AD9203 Drive Configuration
In many cases, particularly in single-supply operation, ac
coupling offers a convenient way of biasing the analog input
signal to the proper signal range. Figure 27 shows a typical
configuration for ac-coupling the analog input signal to the
AD9203. Maintaining the specifications outlined in the data
sheet requires careful selection of the component values. The
most important is the f–3 dB high-pass corner frequency. It is a
function of R2 and the parallel combination of C1 and C2.
00573-027
AIN
R1
R2
VBIAS
VIN
AVDD/2
+
–
C1
C2
AD9203
Figure 27. AC-Coupled Input
The f–3 dB point can be approximated by the equation:
f3dB = 1/(2π × [R2] CEQ)
where CEQ is the parallel combination of C1 and C2. Note that
C1 is typically a large electrolytic or tantalum capacitor that
becomes inductive at high frequencies. Add a small ceramic or
polystyrene capacitor (on the order of 0.01 F) that is negligibly
inductive at higher frequencies while maintaining a low
impedance over a wide frequency range.
There are additional considerations when choosing the resistor
values for an ac-coupled input. The ac-coupling capacitors
integrate the switching transients present at the input of the
AD9203 and cause a net dc bias current, IB, to flow into the
input. The magnitude of the bias current increases as the signal
changes and as the clock frequency increases. This bias current
will result in an offset error of (R1 + R2) IB. If it is necessary to
compensate for this error, consider modifying VBIAS to
account for the resultant offset. In systems that must use dc
coupling, use an op amp to level shift ground-referenced signals
to comply with the input requirements of the AD9203.
OP AMP SELECTION GUIDE
Op amp selection for the AD9203 is highly application
dependent. In general, the performance requirements of any
given application can be characterized by either time domain or
frequency domain constraints. In either case, one should
carefully select an op amp that preserves the performance of the
A/D. This task becomes challenging when one considers the
AD9203’s high performance capabilities coupled with other
system level requirements such as power consumption and cost.
The ability to select the optimal op amp may be further
complicated by either limited power supply availability and/or
limited acceptable supplies for a desired op amp. Newer, high
performance op amps typically have input and output range
limitations in accordance with their lower supply voltages. As a
result, some op amps will be more appropriate in systems where
ac coupling is allowed. When dc coupling is required, the
headroom constraints of op amps (such as rail-to-rail op amps)
or ones where larger supplies can be used, should be
considered.
The following section describes some op amps currently
available from Analog Devices. Please contact the factory or
local sales office for updates on Analog Devices latest amplifier
product offerings.
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| AD9203ARUZRL71 | 制造商:AD 制造商全稱:Analog Devices 功能描述:10-Bit, 40 MSPS, 3 V, 74 mW A/D Converter |
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| AD9203W | 制造商:AD 制造商全稱:Analog Devices 功能描述:10-Bit, 40 MSPS, 3 V, 74 mW Analog-to-Digital Converter |
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