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參數(shù)資料
| 型號： | AD9211BCPZ-300 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 10-Bit, 200 MSPS/250 MSPS/300 MSPS, 1.8 V Analog-to-Digital Converter |
| 中文描述： | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, QCC56 |
| 封裝： | 8 X 8 MM, ROHS COMPLIANT, MO-220VLLD-2, LFCSP-56 |
| 文件頁數(shù)： | 19/28頁 |
| 文件大?。?/td> | 1180K |
| 代理商： | AD9211BCPZ-300 |
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AD9211
THEORY OF OPERATION
The AD9211 architecture consists of a front-end sample and
hold amplifier (SHA) followed by a pipelined switched capacitor
ADC. The quantized outputs from each stage are combined into
a final 10-bit result in the digital correction logic. The pipelined
architecture permits the first stage to operate on a new input
sample, while the remaining stages operate on preceding
samples. Sampling occurs on the rising edge of the clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched capacitor DAC
and interstage residue amplifier (MDAC). The residue amplifier
magnifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each stage to facilitate digital correction
of flash errors. The last stage simply consists of a flash ADC.
The input stage contains a differential SHA that can be ac- or
dc-coupled in differential or single-ended mode. The output-
staging block aligns the data, carries out the error correction,
and passes the data to the output buffers. The output buffers are
powered from a separate supply, allowing adjustment of the
output voltage swing. During power-down, the output buffers
go into a high impedance state.
ANALOG INPUT AND VOLTAGE REFERENCE
The analog input to the AD9211 is a differential buffer. For best
dynamic performance, the source impedances driving VIN+
and VIN should be matched such that common-mode settling
errors are symmetrical. The analog input is optimized to provide
superior wideband performance and requires that the analog
inputs be driven differentially. SNR and SINAD performance
degrades significantly if the analog input is driven with a single-
ended signal.
A wideband transformer, such as Mini-Circuits ADT1-1WT,
can provide the differential analog inputs for applications that
require a single-ended-to-differential conversion. Both analog
inputs are self-biased by an on-chip resistor divider to a
nominal 1.3 V.
An internal differential voltage reference creates positive and
negative reference voltages that define the 1.25 V p-p fixed span
of the ADC core. This internal voltage reference can be adjusted
by means of SPI control. See the AD9211 Configuration Using
the SPI section for more details.
Differential Input Configurations
Optimum performance is achieved while driving the AD9211
in a differential input configuration. For baseband applications,
the
AD8138
differential driver provides excellent performance
and a flexible interface to the ADC. The output common-mode
Rev. 0 | Page 19 of 28
voltage of the AD8138 is easily set to AVDD/2 + 0.5 V, and the
driver can be configured in a Sallen-Key filter topology to
provide band limiting of the input signal.
VIN+
VIN–
AVDD
CML
AD8138
523
499
499
499
33
33
49.9
1V p-p
0.1μF
20pF
AD9211
0
Figure 39. Differential Input Configuration Using the AD8138
At input frequencies in the second Nyquist zone and above, the
performance of most amplifiers may not be adequate to achieve
the true performance of the AD9211. This is especially true in
IF undersampling applications where frequencies in the 70 MHz
to 100 MHz range are being sampled. For these applications,
differential transformer coupling is the recommended input
configuration. The signal characteristics must be considered
when selecting a transformer. Most RF transformers saturate at
frequencies below a few MHz, and excessive signal power can
also cause core saturation, which leads to distortion.
In any configuration, the value of the shunt capacitor, C, is
dependent on the input frequency and may need to be reduced
or removed.
VIN+
VIN–
15
15
50
1.25V p-p
0.1μF
2pF
AD9211
0
Figure 40. Differential Transformer—Coupled Configuration
As an alternative to using a transformer-coupled input at
frequencies in the second Nyquist zone, the
AD8352
differential
driver can be used (see Figure 41).
AD9211
AD8352
0
R
0
C
D
R
D
R
G
0.1μF
0.1μF
0.1μF
VIN+
VIN–
CML
C
0.1μF
0.1μF
16
1
2
3
4
5
11
R
0.1μF
0.1μF
10
8, 13
14
V
CC
200
200
ANALOG INPUT
ANALOG INPUT
0
Figure 41. Differential Input Configuration Using the AD8352
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9211 | 10-Bit, 170/200/250 MSPS 1.8 V A/D Converter |
| AD9211-170EB | 10-Bit, 170/200/250 MSPS 1.8 V A/D Converter |
| AD9211-200EB | 10-Bit, 170/200/250 MSPS 1.8 V A/D Converter |
| AD9211-250EB | 10-Bit, 170/200/250 MSPS 1.8 V A/D Converter |
| AD9211BCPZ-170 | 10-Bit, 170/200/250 MSPS 1.8 V A/D Converter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9212 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Octal, 10-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter |
| AD9212_11 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Octal, 10-Bit, 40 MSPS/65 MSPS, Serial LVDS, 1.8 V ADC |
| AD9212-65EB1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:High Speed ADC USB FIFO Evaluation Kit |
| AD9212-65EBZ | 功能描述:BOARD EVALUATION FOR AD9212 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:- 產(chǎn)品培訓模塊:Obsolescence Mitigation Program 標準包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標準）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
| AD9212ABCPZ-40 | 功能描述:IC ADC 10BIT SRL 40MSPS 64LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應商設備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
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