參數(shù)資料
型號(hào)： AD9212-65EBZ
廠商： Analog Devices, Inc.
英文描述： Octal, 10-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter
中文描述： 八路，10位，六十五分之四十〇 MSPS的串行LVDS 1.8弗吉尼亞州/ D轉(zhuǎn)換器
文件頁(yè)數(shù)： 28/56頁(yè)
文件大?。?/td> 1840K
代理商： AD9212-65EBZ
AD9212
Rev. 0 | Page 28 of 56
SNR
SFDR
0
RBIAS (k
)
S
40
60
50
70
80
90
0
5
10
20
15
25
Figure 63. SNR/SFDR vs. RBIAS, AD9212-40
0
RBIAS (k
)
I
0
0.1
0.4
0.5
0.2
0.3
0.6
0.7
0.8
0
5
10
20
15
25
Figure 64. IAVDD vs. RBIAS, AD9212-40
SNR
SFDR
0
RBIAS (k
)
S
40
60
50
70
80
90
0
5
10
20
15
25
Figure 65. SNR/SFDR vs. RBIAS, AD9212-65
0
RBIAS (k
)
I
0
0.1
0.4
0.5
0.2
0.3
0.6
0.7
0.8
0
5
10
20
15
25
Figure 66. IAVDD vs. RBIAS, AD9212-65
Voltage Reference
A stable and accurate 0.5 V voltage reference is built into the
AD9212. This is gained up by a factor of 2 internally, setting
V
REF
to 1.0 V, which results in a full-scale differential input span
of 2 V p-p. The V
REF
is set internally by default; however, the
VREF pin can be driven externally with a 1.0 V reference to
achieve more accuracy.
When applying the decoupling capacitors to the VREF, REFT,
and REFB pins, use ceramic low ESR capacitors. These capacitors
should be close to the ADC pins and on the same layer of the
PCB as the AD9212. The recommended capacitor values and
configurations for the AD9212 reference pin can be found in
Figure 67.
Table 12. Reference Settings
Selected
Mode
External
Reference
Internal,
2 V p-p FSR
Internal Reference Operation
A comparator within the AD9212 detects the potential at the
SENSE pin and configures the reference. If SENSE is grounded,
the reference amplifier switch is connected to the internal
resistor divider (see Figure 67), setting VREF to 1 V.
The REFT and REFB pins establish their input span of the ADC
core from the reference configuration. The analog input full-
scale range of the ADC equals twice the voltage at the reference
pin for either an internal or an external reference configuration.
If the reference of the AD9212 is used to drive multiple
converters to improve gain matching, the loading of the refer-
ence by the other converters must be considered. Figure 69
depicts how the internal reference voltage is affected by loading.
SENSE
Voltage
AVDD
Resulting
VREF (V)
N/A
Resulting
Differential
Span (V p-p)
2 × external
reference
2.0
AGND to 0.2 V
1.0
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