AVDD = 3.0 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; A
參數(shù)資料
型號(hào): AD9216BCPZRL7-105
廠商: Analog Devices Inc
文件頁數(shù): 23/40頁
文件大?。?/td> 0K
描述: IC ADC 10BIT DL 105MSPS 64-LFCSP
標(biāo)準(zhǔn)包裝: 750
位數(shù): 10
采樣率(每秒): 105M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 2
功率耗散(最大): 330mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 64-LFCSP-VQ(9x9)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 4 個(gè)單端,單極;2 個(gè)差分,單極
配用: AD9216-80PCBZ-ND - BOARD EVAL FOR AD9216 80MSPS
AD9216-105PCBZ-ND - BOARD EVAL FOR AD9216 105MSPS
AD9216
Rev. A | Page 3 of 40
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 3.0 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = 0.5 dBFS differential input, 1.0 V internal reference,
TMIN to TMAX, DCS enabled, unless otherwise noted.
Table 1.
Temp
Test
AD9216BCPZ-65
AD9216BCPZ-80
AD9216BCPZ-105
Parameter
Level
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
RESOLUTION
Full
VI
10
Bits
ACCURACY
No Missing Codes
Full
VI
Guaranteed
Offset Error
Full
VI
-1.9
±0.3
+1.9
-1.9
±0.3
+1.9
2.2
±0.3
+2.2
% FSR
Gain Error1
25°C
VI
-1.6
±0.4
+1.6
-1.6
±0.4
+1.6
1.6
±0.4
+1.6
% FSR
Differential Nonlinearity (DNL)2
Full
IV
-1.0
±0.3
+1.0
-1.0
±0.4
+1.0
1.0
±0.5
+1.0
LSB
25°C
I
-0.9
±0.3
+0.9
-0.9
±0.4
+0.9
1.0
±0.5
+1.0
LSB
Integral Nonlinearity (INL)2
Full
IV
-1.4
±0.5
+1.4
-1.6
±0.5
+1.6
2.5
±1.0
+2.5
LSB
25°C
I
-1.0
±0.5
+1.0
-1.1
±0.5
+1.1
1.5
±1.0
+1.5
LSB
TEMPERATURE DRIFT
Offset Error
Full
V
±10
V/°C
Gain Error1
Full
V
±75
ppm/°C
Reference Voltage
Full
V
±15
ppm/°C
INTERNAL VOLTAGE REFERENCE
Output Voltage Error
Full
VI
±2
±35
±2
±35
±2
±35
mV
Load Regulation @ 1.0 mA
25°C
V
1.0
mV
INPUT REFERRED NOISE
Input Span = 2.0 V
25°C
V
0.5
LSB rms
ANALOG INPUT
Input Span, VREF = 1.0 V
Full
IV
2
V p-p
Input Capacitance3
25°C
V
2
pF
REFERENCE INPUT RESISTANCE
25°C
V
7
k
POWER SUPPLIES
Supply Voltages
AVDD
Full
IV
2.7
3.0
3.3
2.7
3.0
3.3
2.7
3.0
3.3
V
DRVDD
Full
IV
2.25
2.5
3.3
2.25
2.5
3.3
2.25
2.5
3.3
V
Supply Current
Full
VI
72
80
78
85
100
110
mA
Full
VI
15
18
24
mA
PSRR
25°C
V
±0.1
% FSR
POWER CONSUMPTION
PAVDD4
25°C
I
216
240
234
255
300
330
mW
PDRVDD4
25°C
V
38
45
60
mW
Standby Power5
25°C
V
3.0
mW
MATCHING CHARACTERISTICS
Offset Matching Error6
25°C
I
-2.6
±0.2
+2.6
-2.6
±0.2
+2.6
3.5
±0.3
+3.5
% FSR
Gain Matching Error (Shared Reference
Mode)
25°C
I
-0.4
±0.1
+0.4
-0.4
±0.1
+0.4
0.6
±0.1
+0.6
% FSR
Gain Matching Error (Nonshared
Reference Mode)
25°C
I
-1.6
±0.1
+1.6
-1.6
±0.1
+1.6
1.6
±0.3
+1.6
% FSR
1 Gain error and gain temperature coefficient are based on the ADC only (with a fixed 1.0 V external reference).
2 Measured with low frequency ramp at maximum clock rate.
3 Input capacitance refers to the effective capacitance between one differential input pin and AVSS. Refer to Figure
for the equivalent analog input structure.
4 Measured with low frequency analog input at maximum clock rate with approximately 5 pF loading on each output bit.
5 Standby power is measured with the CLK_A and CLK_B pins inactive (that is, set to AVDD or AGND).
6 Both shared reference mode and nonshared reference mode.
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