參數(shù)資料
型號(hào)： AD9218BSTZ-RL105
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 11/28頁(yè)
文件大?。?/td> 0K
描述： IC ADC 10BIT DUAL 105MSPS 48LQFP
標(biāo)準(zhǔn)包裝： 2,000
位數(shù)： 10
采樣率（每秒）： 105M
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 565mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 帶卷 (TR)
輸入數(shù)目和類(lèi)型： 2 個(gè)差分，單極
AD9218
Rev. C | Page 19 of 28
VOLTAGE REFERENCE
APPLICATION INFORMATION
A stable and accurate 1.25 V voltage reference is built into the
AD9218 (VREF OUT). Typically, the internal reference is used
by strapping Pin 5 (REF
The wide analog bandwidth of the AD9218 makes it very
attractive for a variety of high performance receiver and
encoder applications.
A) and Pin 7 (REF
IN
B) to Pin 6
(REF
Figure 44 shows the dual ADC in a
typical low cost I and Q demodulator implementation for cable,
satellite, or wireless LAN modem receivers. The excellent
dynamic performance of the ADC at higher analog input
frequencies and encode rates lets users employ direct IF
sampling techniques. IF sampling eliminates or simplifies analog
mixer and filter stages to reduce total system cost and power.
OUT
). The input range for each channel can be adjusted
independently by varying the reference voltage inputs applied to
the AD9218. No appreciable degradation in performance
occurs when the reference is adjusted ±5%. The full-scale range
of the ADC tracks reference voltage, which changes linearly
(a 5% change in VREF results in a 5% change in full scale).
02
00
1-
04
4
BPF
VCO
IF IN
90°
Q
ADC
I
ADC
AD9218
TIMING
The AD9218 provides latched data outputs, with five pipeline
delays. Data outputs are available one propagation delay (tPD)
after the rising edge of the encode command (see Figure 2
through Figure 4). The length of the output data lines and loads
placed on them should be minimized to reduce transients
within the AD9218. These transients can detract from the
dynamic performance of the converter.
The minimum guaranteed conversion rate is 20 MSPS. At clock
rates below 20 MSPS, dynamic performance degrades.
Figure 44. Typical I/Q Demodulation Scheme
USER SELECT OPTIONS
Two pins are available for a combination of operational modes,
enabling the user to power down both channels, excluding the
reference, or just the B channel. Both modes place the output
buffers in a high impedance state. Recovery from a power-down
state is accomplished in 10 clock cycles following power-on.
The other option allows the user to skew the B channel output
data by one-half a clock cycle. In other words, if two clocks are
fed to the AD9218 and are 180 degrees out of phase, enabling
the data align allows Channel B output data to be available at
the rising edge of Clock A. If the same encode clock is provided
to both channels and the data align pin is enabled, output data
from Channel B is 180 degrees out of phase with respect to
Channel A. If the same encode clock is provided to both
channels and the data align pin is disabled, both outputs are
delivered on the same rising edge of the clock.
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