參數(shù)資料
型號(hào)： AD9221
廠商： Analog Devices, Inc.
元件分類： 串行ADC
英文描述： Complete 12-Bit 1.5/3.0/10.0 MSPS Monolithic A/D Converters
中文描述： 完整的12位1.5/3.0/10.0 MSPS的單片的A / D轉(zhuǎn)換器
文件頁(yè)數(shù)： 22/28頁(yè)
文件大?。?/td> 350K
代理商： AD9221
AD9221/AD9223/AD9220
REV. D
–22–
CML is approximately AVDD/2. This voltage should be buff-
ered if it is to be used for any external biasing.
0.1
m
F
CML
AD9221/
AD9223/
AD9220
22
Figure 57. CML Decoupling
The digital activity on the AD9221/AD9223/AD9220 chip falls
into two general categories: correction logic, and output drivers.
The internal correction logic draws relatively small surges of
current, mainly during the clock transitions. The output drivers
draw large current impulses while the output bits are changing.
The size and duration of these currents are a function of the
load on the output bits: large capacitive loads are to be avoided.
Note, the internal correction logic of the AD9221, AD9223 and
AD9220 is referenced to AVDD while the output drivers are
referenced to DVDD.
The decoupling shown in Figure 58, a 0.1
μ
F ceramic chip
capacitor, is appropriate for a reasonable capacitive load on the
digital outputs (typically 20 pF on each pin). Applications involv-
ing greater digital loads should consider increasing the digital
decoupling proportionally, and/or using external buffers/latches.
0.1
m
F
DVDD
DVSS
28
AD9221/
AD9223/
AD9220
27
Figure 58. Digital Supply Decoupling
A complete decoupling scheme will also include large tantalum
or electrolytic capacitors on the PCB to reduce low-frequency
ripple to negligible levels. Refer to the AD9221/AD9223/
AD9220/EB schematic and layouts in
Figures 62–68 for more
information regarding the placement of decoupling capacitors.
APPLICATIONS
Direct IF Down Conversion Using the AD9220
As previously noted, the AD9220’s performance in the differen-
tial mode of operation extends well beyond its baseband region
and into several Nyquist zone regions. Hence, the AD9220 may
be well suited as a mix down converter in both narrow and
wideband applications. Various IF frequencies exist over the
frequency range in which the AD9220 maintains excellent dy-
namic performance (e.g., refer to Figure 43 and 44). The IF
signal will be aliased to the ADC’s baseband region due to the
sampling process in a similar manner that a mixer will down
convert an IF signal. For signals in various Nyquist zones, the
following equation may be used to determine the final frequency
after aliasing.
f
1 NYQUIST
= f
SIGNAL
f
2 NYQUIST
= f
SAMPLE
– f
SIGNAL
f
3 NYQUIST
= abs (f
SAMPLE
– f
SIGNAL
)
f
4 NYQUIST
= 2
×
f
SAMPLE
– f
SIGNAL
f
5 NYQUIST
= abs (2
f
SAMPLE
– f
SIGNAL
)
There are several potential benefits in using the ADC to alias
(i.e., or mix) down a narrowband or wideband IF signal. First
and foremost is the elimination of a complete mixer stage with
its associated amplifiers and filters, reducing cost and power
dissipation. Second is the ability to apply various DSP techniques
to perform such functions as filtering, channel selection, quadra-
ture demodulation, data reduction, and detection.
One common example is the digitization of a 21.4 MHz IF using a
low jitter 10 MHz sample clock. Using the equation above for
the fifth Nyquist zone, the resultant frequency after sampling is
1.4 MHz. Figure 59 shows the typical performance of the
AD9220 operating under these conditions. Figure 60 demon-
strates how the AD9220 is still able to maintain a high degree of
linearity and SFDR over a wide amplitude.
FREQUENCY – MHz
0
–120
1
5
A
–40
–60
–80
–20
–100
1
7
8
6
9
2
5
3
4
ENCODE = 10MSPS
A
IN
= 21.4MHz
Figure 59. IF Sampling a 21.4 MHz Input Using the
AD9220 (V
CM
= 2.5 V, Input Span = 2 V p-p)
A
IN
– dB
–50
–40
–30
–20
–10
0
90
80
0
S
/
d
40
30
20
10
60
50
70
SFDR
SNR
Figure 60. AD9220 Differential Input SNR/SFDR vs.
Input Amplitude (A
IN
) @ 21.4 MHz
Multichannel Data Acquisition with Autocalibration
The AD9221/AD9223/AD9220 is well suited for high perfor-
mance, low power data acquisition systems. Aside from its ex-
ceptional ac performance, it exhibits true 12-bit linearity and
temperature drift performance (i.e., excluding internal refer-
ence). Furthermore, the A/D product family provides the system
designer with an upward or downward component selection
path based on power consumption and sampling rate.
A typical multichannel data acquisition system is shown in Fig-
ure 61. Also shown is some additional inexpensive gain and
offset autocalibration circuitry which is often required in high
accuracy data acquisition systems. These additional peripheral
components were selected based on their performance, power
consumption, and cost.
相關(guān)PDF資料
PDF描述
AD9221AR RES, 18.2K, 1/4, 1%, MF
AD9221ARS Complete 12-Bit 1.5/3.0/10.0 MSPS Monolithic A/D Converters
AD9223 Complete 12-Bit 1.5/3.0/10.0 MSPS Monolithic A/D Converters
AD9223AR Complete 12-Bit 1.5/3.0/10.0 MSPS Monolithic A/D Converters
AD9224ARS Complete 12-Bit 40 MSPS Monolithic A/D Converter
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AD9221AR-REEL 功能描述:IC ADC 12BIT 1.5MSPS 28-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個(gè)單端，單極；1 個(gè)單端，雙極
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