參數(shù)資料
型號: AD9221AR
廠商: Analog Devices Inc
文件頁數(shù): 5/32頁
文件大?。?/td> 0K
描述: IC ADC 12BIT 1.5MSPS 28-SOIC
標(biāo)準(zhǔn)包裝: 27
位數(shù): 12
采樣率(每秒): 1.5M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 7
功率耗散(最大): 70mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 28-SOIC W
包裝: 管件
輸入數(shù)目和類型: 2 個單端,單極;1 個差分,單極
REV. E
AD9221/AD9223/AD9220
–13–
Table I. Analog Input Configuration Summary
Input
Input Range (V)
Figure
Connection
Coupling
Span (V)
VINA
*
VINB
*
No.
Comments
Single-Ended
DC
2
0 to 2
1
13, 14
Best for stepped input response applica-
tions, suboptimum THD, and noise
performance. Requires
±5 V op amp.
2
× VREF 0 to
VREF
13, 14
Same as above but with improved noise
2
× VREF
performance due to increase in dynamic
range. Headroom/settling time require-
ments of
±5 V op amp should be evaluated.
50 to 5
2.5
13, 14
Optimum noise performance, excellent
THD performance. Requires op amp with
VCC > 5 V due to headroom issue.
2
× VREF 2.5 – VREF
2.5
24
Optimum THD performance with VREF =
to
1. Noise to performance improves while
2.5 + VREF
THD performance degrades as VREF
increases to 2.5 V. Single-supply operation
(i.e., 5 V) for many op amps.
Single-Ended
AC
2 or
0 to 1 or
1 or VREF
15
Suboptimum ac performance due to input
2
× VREF 0 to 2 × VREF
common-mode level not biased at optimum
midsupply level (i.e., 2.5 V).
50 to 5
2.5
15
Optimum noise performance, excellent THD
performance, ability to use
±5 V op amp.
2
× VREF 2.5 – VREF
2.5
16
Flexible input range, optimum THD
to
performance with VREF = 1. Noise
2.5 + VREF
performance improves while THD perfor-
mance degrades as VREF increases to 2.5 V.
Ability to use +5 V or
±5 V op amp.
Differential
AC
2
2 to 3
3 to 2
19
Optimum full-scale THD and SFDR
(via Transformer)
performance well beyond the A/D’s Nyquist
frequency. Preferred mode for under-
sampling applications.
2
× VREF 2.5 – VREF/2 2.5 + VREF/2 19
Same as 2 V to 3 V input range with the
to
exception that full-scale THD and SFDR
2.5 + VREF/2
2.5 – VREF/2
performance can be traded off for better
noise performance. Refer to discussion in AC
Coupling and Interface Issue section and
Simple AC Interface section.
5
1.75 to 3.25
3.25 to 1.75
19
Optimum Noise performance. Also, the
optimum THD and SFDR performance for
“l(fā)ess than” full-scale signals (i.e., –6 dBFS).
Refer to discussion in AC Coupling and
Interface Issue section and Simple AC
Interface section.
*VINA and VINB can be interchanged if signal inversion is required.
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