參數(shù)資料
型號(hào)： AD9222ABCPZ-65
廠商： Analog Devices Inc
文件頁數(shù)： 20/60頁
文件大?。?/td> 0K
描述： IC ADC 12BIT SRL 65MSPS 64LFCSP
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 12
采樣率（每秒）： 65M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 8
功率耗散（最大）： 950.5mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 托盤
輸入數(shù)目和類型： 16 個(gè)單端，單極；8 個(gè)差分，單極
Data Sheet
AD9222
Rev. F | Page 27 of 60
An example of the LVDS output using the ANSI-644 standard
(default) data eye and a time interval error (TIE) jitter histogram
with trace lengths less than 24 inches on standard FR-4 material is
examples of trace lengths exceeding 24 inches on standard FR-4
material. Notice that the TIE jitter histogram reflects the decrease
of the data eye opening as the edge deviates from the ideal position.
It is the user’s responsibility to determine if the waveforms meet
the timing budget of the design when the trace lengths exceed
24 inches. Additional SPI options allow the user to further increase
the internal termination (increasing the current) of all eight outputs
in order to drive longer trace lengths (see Figure 77 and Figure 78).
Even though this produces sharper rise and fall times on the data
edges and is less prone to bit errors, the power dissipation of the
DRVDD supply increases when this option is used.
In cases that require increased driver strength to the DCO± and
FCO± outputs because of load mismatch, Register 0x15 allows
the user to increase the drive strength by 2×. To do this, set the
appropriate bit in Register 0x5. Note that this feature cannot be
used with Bit 4 and Bit 5 in Register 0x15. Bit 4 and Bit 5 take
precedence over this feature. See the Memory Map section for
more details.
500
400
300
200
100
–500
–400
–300
–200
–100
0
–1.0ns
–1.5ns
–0.5ns
0ns
0.5ns
1.0ns
1.5ns
EYE
D
IA
G
R
A
M
VO
L
T
A
G
E
(m
V)
EYE: ALL BITS
ULS: 12071/12071
90
50
10
20
30
40
60
70
80
0
–150ps
–100ps
–50ps
0ps
50ps
100ps
150ps
TIE
J
ITTE
R
H
IS
TOGR
A
M
(
H
it
s
)
05967-
061
Figure 73. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths
Less than 24 Inches on Standard FR-4, AD9222-50
600
400
200
–600
–400
–200
0
–1.0ns
–1.5ns
–0.5ns
0ns
0.5ns
1.0ns
1.5ns
EYE
D
IA
G
R
A
M
VO
L
T
A
G
E
(m
V)
EYE: ALL BITS
ULS: 9596/15596
20
40
60
80
100
140
120
0
–150ps
–100ps
–50ps
0ps
50ps
100ps
150ps
TIE
J
ITTE
R
H
IS
TOGR
A
M
(
H
it
s
)
05967-
106
Figure 74. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths
Less than 24 Inches on Standard FR-4, AD9222-65
60
80
90
70
50
40
20
10
100
30
0
–200ps
–100ps
100ps
0ps
200ps
TIE
J
ITTE
R
H
IS
TOGR
A
M
(
H
it
s
)
500
400
300
200
100
–500
–400
–300
–200
–100
0
–1.0ns
–0.5ns
0ns
0.5ns
1.5ns
–1.5ns
1.0ns
EYE
D
IA
G
R
A
M
VO
L
T
A
G
E
(m
V)
EYE: ALL BITS
ULS: 12067/12067
05967-
059
Figure 75. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths
Greater than 24 Inches on Standard FR-4, AD9222-50
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