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參數(shù)資料
| 型號： | AD9223 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 串行ADC |
| 英文描述： | Complete 12-Bit 1.5/3.0/10.0 MSPS Monolithic A/D Converters |
| 中文描述： | 完整的12位1.5/3.0/10.0 MSPS的單片的A / D轉(zhuǎn)換器 |
| 文件頁數(shù)： | 19/28頁 |
| 文件大?。?/td> | 350K |
| 代理商： | AD9223 |
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AD9221/AD9223/AD9220
REV. D
–19–
1.5 V. This sets the input span to be 3 V p-p. To assure stabil-
ity, place a 0.1
μ
F ceramic capacitor in parallel with R1.
The common-mode voltage can be set to VREF by connecting
VINB to VREF to provide an input span of 0 to 2
×
VREF.
Alternatively, the common-mode voltage can be set to VREF
by connecting VINB to a low impedance 2.5 V source. For
the example shown, the valid input single range for VINA is 1 V
to 4 V since VINB is set to an external, low impedance 2.5 V
source. The VREF pin should be bypassed to the REFCOM pin
with a 10
μ
F tantalum capacitor in parallel with a low induc-
tance 0.1
μ
F ceramic capacitor.
1.5V
C1
0.1
m
F
10
m
F
VINA
VINB
VREF
SENSE
REFCOM
AD9220
4V
1V
2.5V
R1
2.5k
V
R2
5k
V
0.1
m
F
Figure 49. Resistor Programmable Reference—3 V p-p
Input Span, V
CM
= 2.5 V
USING AN EXTERNAL REFERENCE
Using an external reference may enhance the dc performance of
the AD9221/AD9223/AD9220 by improving drift and accuracy.
Figures 50 through 52 show examples of how to use an external
reference with the A/D. Table III is a list of suitable voltage
references from Analog Devices. To use an external reference,
the user must disable the internal reference amplifier and drive
the VREF pin. Connecting the SENSE pin to AVDD disables
the internal reference amplifier.
Table III. Suitable Voltage References
Initial
Accuracy
% (max)
Operating
Current
(
m
A)
Output
Voltage
Drift
(ppm/
8
C)
Internal
AD589
AD1580
REF191
Internal
REF192
REF43
AD780
1.00
1.235
1.225
2.048
2.50
2.50
2.50
2.50
26
10–100
50–100
5–25
26
5–25
10–25
3–7
1.4
1.2–2.8
0.08–0.8
0.1–0.5
1.4
0.08–0.4
0.06–0.1
0.04–0.2
N/A
50
50
45
N/A
45
600
1000
The AD9221/AD9223/AD9220 contains an internal reference
buffer, A2 (see Figure 35), that simplifies the drive requirements
of an external reference. The external reference must be able to
drive a
≈
5 k
(
±
20%) load. Note that the bandwidth of the ref-
erence buffer is deliberately left small to minimize the reference
noise contribution. As a result, it is not possible to change the
reference voltage rapidly in this mode without the removal of
the CAPT/CAPB Decoupling Network.
Variable Input Span with V
CM
= 2.5 V
Figure 50 shows an example of the AD9221/AD9223/AD9220
configured for an input span of 2
×
VREF centered at 2.5 V. An
external 2.5 V reference drives the VINB pin thus setting the
common-mode voltage at 2.5 V. The input span can be inde-
pendently set by a voltage divider consisting of R1 and R2
which generates the VREF signal. A1 buffers this resistor net-
work and drives VREF. Choose this op amp based on accuracy
requirements. It is essential that a minimum of a 10
μ
F capaci-
tor in parallel with a 0.1
μ
F low inductance ceramic capacitor
decouple the reference output to ground.
2.5V+VREF
2.5V–VREF
2.5V
+5V
0.1
m
F
22
m
F
VINA
VINB
VREF
SENSE
+5V
R2
0.1
m
F
A1
R1
0.1
m
F
2.5V
REF
AD9221/
AD9223/
AD9220
Figure 50. External Reference—V
CM
= 2.5 V (2.5 V on
VINB, Resistor Divider to Make VREF)
Single-Ended Input with 0 to 2
3
VREF Range
Figure 51 shows an example of an external reference driving
both VINB and VREF. In this case, both the common mode
voltage and input span are directly dependent on the value of
VREF. More specifically, the common mode voltage is equal to
VREF while the input span is equal to 2
×
VREF. Thus, the
valid input range extends from 0 to 2
×
VREF. For example, if
the REF-191, a 2.048 external reference was selected, the valid
input range extends from 0 to 4.096 V. In this case, 1 LSB of
the AD9221/AD9223/AD9220 corresponds to 1 mV. It is es-
sential that a minimum of a 10
μ
F capacitor in parallel with a
0.1
μ
F low inductance ceramic capacitor decouple the reference
output to ground.
2
3
REF
0V
+5V
10
m
F
VINA
VINB
VREF
SENSE
AD9221/
AD9223/
AD9220
+5V
0.1
m
F
VREF
0.1
m
F
0.1
m
F
Figure 51. Input Range = 0 V to 2
×
VREF
Low Cost/Power Reference
The external reference circuit shown in Figure 52 uses a low
cost 1.225 V external reference (e.g., AD580 or AD1580) along
with an op amp and transistor. The 2N2222 transistor acts in
conjunction with 1/2 of an OP282 to provide a very low imped-
ance drive for VINB. The selected op amp need not be a high
speed op amp and may be selected based on cost, power and
accuracy.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9223AR | 制造商:Analog Devices 功能描述:ADC Single Pipelined 3Msps 12-bit Parallel 28-Pin SOIC W 制造商:Rochester Electronics LLC 功能描述:12-BIT, 1.5/3.0/10 MSPS A/D CONVERTER - Bulk 制造商:Analog Devices 功能描述:IC 12-BIT ADC |
| AD9223AR-REEL | 制造商:Analog Devices 功能描述:ADC Single Pipelined 3Msps 12-bit Parallel 28-Pin SOIC W T/R |
| AD9223ARS | 制造商:Analog Devices 功能描述:ADC Single Pipelined 3Msps 12-bit Parallel 28-Pin SSOP 制造商:Analog Devices 功能描述:IC 12-BIT ADC |
| AD9223ARS-REEL | 制造商:Analog Devices 功能描述:ADC Single Pipelined 3Msps 12-bit Parallel 28-Pin SSOP T/R |
| AD9223ARSZ | 功能描述:IC ADC 12BIT 3.0MSPS 28-SSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:microPOWER™ 位數(shù):8 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:- 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-VQFN 裸露焊盤（4x4） 包裝:Digi-Reel® 輸入數(shù)目和類型:8 個單端，單極 產(chǎn)品目錄頁面:892 (CN2011-ZH PDF) 其它名稱:296-25851-6 |
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