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參數(shù)資料
| 型號： | AD9225ARS |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/25頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 25MSPS 28-SSOP |
| 標準包裝： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 25M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 7 |
| 功率耗散（最大）： | 373mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.209"，5.30mm 寬） |
| 供應商設備封裝： | 28-SSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 2 個單端，雙極；1 個差分，單極 |
–18–
AD9225
Table V. Out-of-Range Truth Table
OTR
MSB
Analog Input Is
00
In Range
01
In Range
10
Underrange
11
Overrange
OVER = “1”
UNDER = “1”
MSB
OTR
MSB
Figure 23. Overrange or Underrange Logic
Digital Output Driver Considerations (DRVDD)
The AD9225 output drivers can be configured to interface with
5 V or 3.3 V logic families by setting DRVDD to 5 V or 3.3 V,
respectively. The output drivers are sized to provide sufficient
output current to drive a wide variety of logic families. However,
large drive currents tend to cause glitches on the supplies and may
affect SINAD performance. Applications requiring the ADC to
drive large capacitive loads or large fanout may require additional
decoupling capacitors on DRVDD. In extreme cases, external
buffers or latches may be required.
Clock Input and Considerations
The AD9225 internal timing uses the two edges of the clock input
to generate a variety of internal timing signals. The clock input
must meet or exceed the minimum specified pulse width high and
low (tCH and tCL) specifications for the given ADC as defined in
the Switching Specifications table to meet the rated performance
specifications. For example, the clock input to the AD9225 operat-
ing at 25 MSPS may have a duty cycle between 45% to 55% to
meet this timing requirement since the minimum specified tCH and
tCL is 18 ns. For low clock rates, the duty cycle may deviate from
this range to the extent that both tCH and tCL are satisfied.
All high speed high resolution ADCs are sensitive to the quality of
the clock input. The degradation in SNR at a given full-scale input
frequency (fIN) due to only aperture jitter (tA) can be calculated
with the following equation:
SNR
= 20 log10
1
2
p f IN tA
˙
In the equation, the rms aperture jitter, tA, represents the root-
sum square of all the jitter sources, which include the clock
input, analog input signal, and ADC aperture jitter specification.
Undersampling applications are particularly sensitive to jitter.
Clock input should be treated as an analog signal in cases where
aperture jitter may affect the dynamic range of the AD9225. Power
supplies for clock drivers should be separated from the ADC out-
put driver supplies to avoid modulating the clock signal with digital
noise. Low jitter crystal controlled oscillators make the best clock
sources. If the clock is generated from another type of source (by
gating, dividing, or other method), it should be retimed by the
original clock at the last step.
The clock input is referred to as the analog supply. Its logic thresh-
old is AVDD/2. If the clock is being generated by 3 V logic, it will
have to be level shifted into 5 V CMOS logic levels. This can also
be accomplished by ac coupling and level-shifting the clock signal.
The AD9225 has a clock tolerance of 5% at 25 MHz. One way to
obtain a 50% duty cycle clock is to divide down a clock of higher
frequency, as shown in Figure 24. This configuration will also
decrease the jitter of the source clock.
+5V
R
D
Q
S
+5V
50MHz
25MHz
Figure 24. Divide-by-Two Clock Circuit
In this case, a 50 MHz clock is divided by two to produce the
25 MHz clock input for the AD9225. In this configuration, the
duty cycle of the 50 MHz clock is irrelevant.
The input circuitry for the CLOCK pin is designed to accommo-
date CMOS inputs. The quality of the logic input, particularly
the rising edge, is critical in realizing the best possible jitter
performance of the part; the faster the rising edge, the better
the jitter performance.
As a result, careful selection of the logic family for the clock driver,
as well as the fanout and capacitive load on the clock line, is impor-
tant. Jitter-induced errors become more predominant at higher
frequency and large amplitude inputs, where the input slew rate
is greatest.
Most of the power dissipated by the AD9225 is from the analog
power supplies. However, lower clock speeds will reduce digital
current. Figure 25 shows the relationship between power and
clock rate.
SAMPLE RATE
380
360
340
320
300
035
5
POWER
(mW)
10
15
280
260
240
220
200
180
30
20
25
2V
INTERNAL
REFERENCE
1V
INTERNAL
REFERENCE
Figure 25. Power Consumption vs. Clock Rate
Direct IF Down Conversion Using the AD9225
Sampling IF signals above an ADC’s baseband region (i.e.,
dc to fS/2) is becoming increasingly popular in communication
applications. This process is often referred to as direct IF down
conversion or undersampling. There are several potential benefits
in using the ADC to alias (i.e., or mix) down a narrowband or
wideband IF signal. First and foremost is the elimination of a
complete mixer stage with its associated baseband amplifiers and
filters, reducing cost and power dissipation. Second is the ability to
apply various DSP techniques to perform such functions as filter-
ing, channel selection, quadrature demodulation, data reduction,
Rev. C
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD9225ARSRL | 功能描述:IC ADC 12BIT 25MSPS 28-SSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個單端，單極；1 個單端，雙極 |
| AD9225ARSZ | 功能描述:IC ADC 12BIT 25MSPS 28-SSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:1 系列:microPOWER™ 位數(shù):8 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:- 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應商設備封裝:24-VQFN 裸露焊盤（4x4） 包裝:Digi-Reel® 輸入數(shù)目和類型:8 個單端，單極 產(chǎn)品目錄頁面:892 (CN2011-ZH PDF) 其它名稱:296-25851-6 |
| AD9225ARSZ | 制造商:Analog Devices 功能描述:IC 制造商:Analog Devices 功能描述:IC, ADC, 12BIT, 25MSPS, SSOP-28 |
| AD9225ARSZRL | 功能描述:IC ADC 12BIT 25MSPS 28SSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個單端，單極；1 個單端，雙極 |
| AD9225ARZ | 功能描述:IC ADC 12BIT 25MSPS 28-SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:1 系列:microPOWER™ 位數(shù):8 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:- 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應商設備封裝:24-VQFN 裸露焊盤（4x4） 包裝:Digi-Reel® 輸入數(shù)目和類型:8 個單端，單極 產(chǎn)品目錄頁面:892 (CN2011-ZH PDF) 其它名稱:296-25851-6 |
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