參數(shù)資料
型號: AD9226AST
廠商: Analog Devices Inc
文件頁數(shù): 25/28頁
文件大?。?/td> 0K
描述: IC ADC 12BIT 65MSPS 48-LQFP
產(chǎn)品變化通告: Product Discontinuance 27/Oct/2011
標(biāo)準(zhǔn)包裝: 1
位數(shù): 12
采樣率(每秒): 65M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 3
功率耗散(最大): 475mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-LQFP(7x7)
包裝: 托盤
輸入數(shù)目和類型: 2 個單端,單極;1 個差分,單極
REV. B
AD9226
–6–
48-PIN FUNCTION DESCRIPTIONS
Pin
Number
Name
Description
1, 2, 32, 33 AVSS
Analog Ground
3, 4, 31, 34 AVDD
5 V Analog Supply
5, 6, 8, 10, NC
No Connect
11, 44
7
CLK
Clock Input Pin
9
OEB
Output Enable (Active Low)
12
BIT 12
Least Significant Data Bit (LSB)
13
BIT 11
Data Output Bit
14, 22, 30
DRVSS
Digital Output Driver Ground
15, 23, 29
DRVDD
3 V to 5 V Digital Output
Driver Supply
16–21,
BITS 10–5,
Data Output Bits
24–26
BITS 4–2
27
BIT 1
Most Significant Data Bit (MSB)
28
OTR
Out of Range
35
MODE2
Data Format Select
36
SENSE
Reference Select
37
VREF
Reference In/Out
38
REFCOM
Reference Common
(AVSS)
39, 40
CAPB
Noise Reduction Pin
41, 42
CAPT
Noise Reduction Pin
43
MODE1
Clock Stabilizer
45
CM LEVEL
Midsupply Reference
46
VINA
Analog Input Pin (+)
47
VINB
Analog Input Pin (–)
48
VR
Noise Reduction Pin
PIN CONNECTION
28-Lead SSOP
TOP VIEW
(Not to Scale)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AD9226
OTR
(MSB) BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
CLK
(LSB) BIT 12
BIT 11
BIT 10
BIT 7
BIT 8
BIT 9
AVDD
AVSS
SENSE
VREF
REFCOM (AVSS)
CAPB
CAPT
DRVDD
DRVSS
AVDD
AVSS
MODE
VINA
VINB
PIN CONNECTION
48-Lead LQFP
36
35
34
33
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
48 47 46 45 44
39 38 37
43 42 41 40
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
SENSE
MODE2
AVDD
AVSS
AVDD
DRVSS
AVSS
AVDD
NC
CLK
NC = NO CONNECT
NC
OEB
NC
DRVDD
OTR
BIT 1 (MSB)
BIT 2
AD9226
(LSB) BIT 12
BIT 3
VR
VINB
VINA
CM
LEVEL
NC
MODE1
CAPT
CAPB
REF
COM
(AVSS)
VREF
BIT
11
DRVSS
DRVDD
BIT
10
BIT
9
BIT
8
BIT
7
BIT
6
BIT
5
DRVSS
DRVDD
BIT
4
28-PIN FUNCTION DESCRIPTIONS
Pin
Number
Name
Description
1
CLK
Clock Input Pin
2
BIT 12
Least Significant Data Bit (LSB)
3–12
BITS 11–2
Data Output Bits
13
BIT 1
Most Significant Data Bit (MSB)
14
OTR
Out of Range
15, 26
AVDD
5 V Analog Supply
16, 25
AVSS
Analog Ground
17
SENSE
Reference Select
18
VREF
Input Span Select (Reference I/O)
19
REFCOM
Reference Common
(AVSS)
20
CAPB
Noise Reduction Pin
21
CAPT
Noise Reduction Pin
22
MODE
Data Format Select /Clock Stabilizer
23
VINA
Analog Input Pin (+)
24
VINB
Analog Input Pin (–)
27
DRVSS
Digital Output Driver Ground
28
DRVDD
3 V to 5 V Digital Output
Driver Supply
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