參數(shù)資料
型號(hào)： AD9228-65EB
廠商： Analog Devices, Inc.
英文描述： Quad, 12-bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter
中文描述： 四，12位，六十五分之四十○MSPS的串行LVDS 1.8弗吉尼亞州/ D轉(zhuǎn)換器
文件頁(yè)數(shù)： 34/52頁(yè)
文件大?。?/td> 1659K
代理商： AD9228-65EB
AD9228
Power and Ground Recommendations
When connecting power to the AD9228, it is recommended
that two separate 1.8 V supplies be used: one for analog (AVDD)
and one for digital (DRVDD). If only one supply is available, it
should be routed to the AVDD first and then tapped off and
isolated with a ferrite bead or a filter choke preceded by
decoupling capacitors for the DRVDD. The user can employ
several different decoupling capacitors to cover both high and
low frequencies. These should be located close to the point of
entry at the PC board level and close to the parts with minimal
trace length.
Rev. 0 | Page 34 of 52
A single PC board ground plane should be sufficient when
using the AD9228. With proper decoupling and smart parti-
tioning of the PC board’s analog, digital, and clock sections,
optimum performance is easily achieved.
Exposed Paddle Thermal Heat Slug Recommendations
It is required that the exposed paddle on the underside of the
ADC is connected to analog ground (AGND) to achieve the
best electrical and thermal performance of the AD9228. An
exposed continuous copper plane on the PCB should mate to
the AD9228 exposed paddle, Pin 0. The copper plane should
have several vias to achieve the lowest possible resistive thermal
path for heat dissipation to flow through the bottom of the PCB.
These vias should be solder filled or plugged.
To maximize the coverage and adhesion between the ADC and
PCB, partition the continuous copper plane by overlaying a
silkscreen on the PCB into several uniform sections. This provides
several tie points between the two during the reflow process.
Using one continuous plane with no partitions only guarantees
one tie point between the ADC and PCB. See Figure 69 for a
PCB layout example. For detailed information on packaging
and the PCB layout of chip scale packages, see the
AN-772
Application Note
, “A Design and Manufacturing Guide for the
Lead Frame Chip Scale Package (LFCSP),” at
www.analog.com
.
SILKSCREEN PARTITION
PIN 1 INDICATOR
0
-
Figure 69. Typical PCB Layout
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相關(guān)代理商/技術(shù)參數(shù)
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