參數資料
型號： AD9231BCPZRL7-65
廠商： Analog Devices Inc
文件頁數： 20/36頁
文件大?。?/td> 0K
描述： IC ADC 12BIT 65MSPS 64LFCSP
標準包裝： 750
位數： 12
采樣率（每秒）： 65M
數據接口： 串行，SPI?
轉換器數目： 2
功率耗散（最大）： 143.8mW
電壓電源： 模擬和數字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應商設備封裝： 64-LFCSP-VQ（9x9）
包裝： 帶卷 (TR)
輸入數目和類型： 4 個單端，單極；2 個差分，單極
AD9231
Rev. A | Page 27 of 36
BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST
The AD9231 includes a built-in self-test feature designed to
enable verification of the integrity of each channel as well as to
facilitate board level debugging. A built-in self-test (BIST) feature
that verifies the integrity of the digital datapath of the AD9231
is included. Various output test options are also provided to place
predictable values on the outputs of the AD9231.
BUILT-IN SELF-TEST (BIST)
The BIST is a thorough test of the digital portion of the selected
AD9231 signal path. Perform the BIST test after a reset to ensure
the part is in a known state. During BIST, data from an internal
pseudorandom noise (PN) source is driven through the digital
datapath of both channels, starting at the ADC block output.
At the datapath output, CRC logic calculates a signature from
the data. The BIST sequence runs for 512 cycles and then stops.
Once completed, the BIST compares the signature results with a
pre-determined value. If the signatures match, the BIST sets Bit 0
of Register 0x24, signifying the test passed. If the BIST test failed,
Bit 0 of Register 0x24 is cleared. The outputs are connected
during this test, so the PN sequence can be observed as it runs.
Writing the value 0x05 to Register 0x0E runs the BIST. This enables
the Bit 0 (BIST enable) of Register 0x0E and resets the PN sequence
generator, Bit 2 (BIST INIT) of Register 0x0E. At the completion of
the BIST, Bit 0 of Register 0x24 is automatically cleared. The PN
sequence can be continued from its last value by writing a 0 in
Bit 2 of Register 0x0E. However, if the PN sequence is not reset,
the signature calculation does not equal the predetermined
value at the end of the test. At that point, the user needs to rely
on verifying the output data.
OUTPUT TEST MODES
The output test options are described in Table 16 at Address
0x0D. When an output test mode is enabled, the analog section
of the ADC is disconnected from the digital back-end blocks
and the test pattern is run through the output formatting block.
Some of the test patterns are subject to output formatting, and
some are not. The PN generators from the PN sequence tests
can be reset by setting Bit 4 or Bit 5 of Register 0x0D. These
tests can be performed with or without an analog signal (if
present, the analog signal is ignored), but they do require
an encode clock. For more information, see the AN-877
Application Note, Interfacing to High Speed ADCs via SPI.
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相關代理商/技術參數
參數描述
AD9231BCPZRL7-80 功能描述:IC ADC 12BIT 80MSPS 64LFCSP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 標準包裝:1 系列:- 位數:14 采樣率（每秒）:83k 數據接口:串行，并聯(lián) 轉換器數目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應商設備封裝:28-PDIP 包裝:管件 輸入數目和類型:1 個單端，雙極
AD9233 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Analog-to-Digital Converter
AD9233-105EB 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Analog-to-Digital Converter
AD9233-105EBZ 制造商:Analog Devices 功能描述:
AD9233-125EB 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Analog-to-Digital Converter
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