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參數(shù)資料
| 型號： | AD9235BCP-65 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 12-Bit, 20/40/65 MSPS 3 V A/D Converter |
| 中文描述： | 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, QCC32 |
| 封裝： | MO-220-VHHD-2, LFCSP-32 |
| 文件頁數(shù)： | 2/32頁 |
| 文件大小： | 1181K |
| 代理商： | AD9235BCP-65 |
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REV. B
–2–
AD9235–SPECIFICATIONS
DC SPECIFICATIONS
Test
Level
AD9235BRU-20
Min Typ
AD9235BRU-40
Min Typ
AD9235BRU/BCP-65
Min Typ
Parameter
Temp
Max
Max
Max
Unit
RESOLUTION
Full
VI
12
12
12
Bits
ACCURACY
No Missing Codes Guaranteed
Offset Error
Gain Error
1
Differential Nonlinearity (DNL)
2
Full
Full
Full
Full
25
°
C
Full
25
°
C
VI
VI
VI
IV
I
IV
I
12
12
12
Bits
% FSR
% FSR
LSB
LSB
LSB
LSB
±
0.30
±
0.30
±
0.35
±
0.35
±
0.45
±
0.40
±
1.20
±
2.40
±
0.65
±
0.50
±
0.50
±
0.35
±
0.35
±
0.50
±
0.40
±
1.20
±
2.50
±
0.75
±
0.50
±
0.50
±
0.40
±
0.35
±
0.70
±
0.45
±
1.20
±
2.60
±
0.80
Integral Nonlinearity (INL)
2
±
0.80
±
0.90
±
1.30
TEMPERATURE DRIFT
Offset Error
Gain Error
1
Full
Full
V
V
±
2
±
12
±
2
±
12
±
3
±
12
ppm/
°
C
ppm/
°
C
INTERNAL VOLTAGE
REFERENCE
Output Voltage Error (1 V Mode)
Load Regulation @ 1.0 mA
Output Voltage Error (0.5 V Mode)
Load Regulation @ 0.5 mA
Full
Full
Full
Full
VI
V
V
V
±
5
0.8
±
2.5
0.1
±
35
±
5
0.8
±
2.5
0.1
±
35
±
5
0.8
±
2.5
0.1
±
35
mV
mV
mV
mV
INPUT REFERRED NOISE
VREF = 0.5 V
VREF = 1.0 V
25
°
C
25
°
C
V
V
0.54
0.27
0.54
0.27
0.54
0.27
LSB rms
LSB rms
ANALOG INPUT
Input Span, VREF = 0.5 V
Input Span, VREF = 1.0 V
Input Capacitance
3
Full
Full
Full
IV
IV
V
1
2
7
1
2
7
1
2
7
V p-p
V p-p
pF
REFERENCE INPUT
RESISTANCE
Full
V
7
7
7
k
POWER SUPPLIES
Supply Voltages
AVDD
DRVDD
Supply Current
IAVDD
2
IDRVDD
2
PSRR
Full
Full
IV
IV
2.7
2.25 3.0
3.0
3.6
3.6
2.7
2.25 3.0
3.0
3.6
3.6
2.7
2.25 3.0
3.0
3.6
3.6
V
V
Full
Full
Full
V
V
V
30
2
±
0.01
55
5
±
0.01
100
7
±
0.01
mA
mA
% FSR
POWER CONSUMPTION
DC Input
4
Sine Wave Input
2
Standby Power
5
Full
Full
Full
V
VI
V
90
95
1.0
165
180
1.0
300
320
1.0
mW
mW
mW
110
205
350
NOTES
1
Gain error and gain temperature coefficient are based on the ADC only (with a fixed 1.0 V external reference).
2
Measured at maximum clock rate, f
= 2.4 MHz, full-scale sine wave, with approximately 5 pF loading on each output bit.
3
Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 2 for the equivalent analog input structure.
4
Measured with dc input at maximum clock rate.
5
Standby power is measured with a dc input, the CLK pin inactive (i.e., set to AVDD or AGND).
Specifications subject to change without notice.
(AVDD = 3 V, DRVDD = 2.5 V, Maximum Sample Rate, 2 V p-p Differential Input,
1.0 V internal reference, T
MIN
to T
MAX
, unless otherwise noted.)
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