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| 型號(hào)： | AD9235BCPZ-65 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 65MSPS 32-LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 65M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 3 |
| 功率耗散（最大）： | 300mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-VQ（5x5） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 2 個(gè)單端，單極；1 個(gè)差分，單極 |
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Data Sheet
AD9235
Rev. D | Page 15 of 40
APPLYING THE AD9235
THEORY OF OPERATION
The AD9235 architecture consists of a front end SHA followed
by a pipelined switched capacitor ADC. The pipelined ADC is
divided into three sections, consisting of a 4-bit first stage
followed by eight 1.5-bit stages and a final 3-bit flash. Each stage
provides sufficient overlap to correct for flash errors in the
preceding stages. The quantized outputs from each stage are
combined into a final 12-bit result in the digital correction log-
ic. The pipelined architecture permits the first stage to operate
on a new input sample while the remaining stages operate on
preceding samples. Sampling occurs on the rising edge
of the clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched capacitor DAC
and interstage residue amplifier (MDAC). The residue amplifier
magnifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each stage to facilitate digital correction
of flash errors. The last stage simply consists of a flash ADC.
The input stage contains a differential SHA that can be ac- or
dc-coupled in differential or single-ended modes. The output-
staging block aligns the data, carries out the error correction,
and passes the data to the output buffers. The output buffers are
powered from a separate supply, allowing adjustment of the
output voltage swing. During power-down, the output buffers
go into a high impedance state.
ANALOG INPUT
The analog input to the AD9235 is a differential switched
capacitor SHA that has been designed for optimum perfor-
mance while processing a differential input signal. The SHA
input can support a wide common-mode range and maintain
excellent performance, as shown in Figure 34. An input
common-mode voltage of midsupply minimizes signal-
dependent errors and provides optimum performance.
Referring to Figure 33, the clock signal alternatively switches
the SHA between sample mode and hold mode. When the SHA
is switched into sample mode, the signal source must be capable
of charging the sample capacitors and settling within one-half
of a clock cycle. A small resistor in series with each input can
help reduce the peak transient current required from the output
stage of the driving source. Also, a small shunt capacitor can be
placed across the inputs to provide dynamic charging currents.
This passive network creates a low-pass filter at the ADC’s
input; therefore, the precise values are dependent upon the
application. In IF undersampling applications, any shunt
capacitors should be removed. In combination with the driving
source impedance, they would limit the input bandwidth.
For best dynamic performance, the source impedances driving
VIN+ and VIN– should be matched such that common-mode
settling errors are symmetrical. These errors are reduced by the
common-mode rejection of the ADC.
VIN+
VIN–
CPAR
5pF
T
02461-033
H
T
H
Figure 33. Switched-Capacitor SHA Input
An internal differential reference buffer creates positive and
negative reference voltages, REFT and REFB, respectively, that
define the span of the ADC core. The output common mode of
the reference buffer is set to midsupply, and the REFT and
REFB voltages and span are defined as:
REFT = (AVDD + VREF)
REFB = (AVDD VREF)
Span = 2 × (REFT REFB) = 2 × VREF
It can be seen from the equations above that the REFT and
REFB voltages are symmetrical about the midsupply voltage
and, by definition, the input span is twice the value of the
VREF voltage.
02461-034
COMMON-MODE LEVEL (V)
3.0
0
0.5
1.0
1.5
2.0
2.5
THD
(dBc)
–50
–90
–75
–80
–85
–55
–60
–65
–70
SNR
(dBc)
90
85
80
75
70
65
60
55
50
SNR 35MHz 2V DIFF
THD 35MHz 2V DIFF
THD 2.5MHz 2V DIFF
SNR 2.5MHz 2V DIFF
Figure 34. AD9235-65: SNR, THD vs. Common-Mode Level
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