參數(shù)資料
型號(hào)： AD9235BRU-65
廠商： ANALOG DEVICES INC
元件分類(lèi)： ADC
英文描述： 12-Bit, 20/40/65 MSPS 3 V A/D Converter
中文描述： 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
封裝： MO-153-AE, TSSOP-28
文件頁(yè)數(shù)： 13/32頁(yè)
文件大?。?/td> 1181K
代理商： AD9235BRU-65
REV. B
–13–
AD9235
APPLYING THE AD9235
THEORY OF OPERATION
The AD9235 architecture consists of a front-end sample and
hold amplifier (SHA) followed by a pipelined switched capacitor
ADC. The pipelined ADC is divided into three sections, consisting
of a 4-bit first stage followed by eight 1.5-bit stages and a final 3-bit
flash. Each stage provides sufficient overlap to correct for flash
errors in the preceding stages. The quantized outputs from each
stage are combined into a final 12-bit result in the digital correction
logic. The pipelined architecture permits the first stage to operate
on a new input sample while the remaining stages operate on pre-
ceding samples. Sampling occurs on the rising edge of the clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched capacitor DAC
and interstage residue amplifier (MDAC). The residue amplifier
magnifies the difference between the reconstructed DAC output and
the flash input for the next stage in the pipeline. One bit of redun-
dancy is used in each stage to facilitate digital correction of flash
errors. The last stage simply consists of a flash ADC.
The input stage contains a differential SHA that can be ac- or
dc-coupled in differential or single-ended modes. The output-
staging block aligns the data, carries out the error correction, and
passes the data to the output buffers. The output buffers are
powered from a separate supply, allowing adjustment of the
output voltage swing. During power-down, the output buffers
go into a high impedance state.
ANALOG INPUT
The analog input to the AD9235 is a differential switched
capacitor SHA that has been designed for optimum performance
while processing a differential input signal. The SHA input can
support a wide common-mode range and maintain excellent
performance, as shown in Figure 7. An input common-mode
voltage of midsupply will minimize signal-dependant errors and
provide optimum performance.
Referring to Figure 6, the clock signal alternatively switches the
SHA between sample mode and hold mode. When the SHA is
switched into sample mode, the signal source must be capable
of charging the sample capacitors and settling within one-half of
a clock cycle. A small resistor in series with each input can help
reduce the peak transient current required from the output stage
of the driving source. Also, a small shunt capacitor can be placed
across the inputs to provide dynamic charging currents. This
passive network will create a low-pass filter at the ADC’s input;
therefore, the precise values are dependant upon the application.
In IF undersampling applications, any shunt capacitors should
be removed. In combination with the driving source impedance,
they would limit the input bandwidth.
For best dynamic performance, the source impedances driving
VIN+ and VIN– should be matched such that common-mode
settling errors are symmetrical. These errors will be reduced by
the common-mode rejection of the ADC.
H
H
VIN+
VIN–
C
PAR
C
PAR
T
T
5pF
5pF
T
T
Figure 6. Switched-Capacitor SHA Input
An internal differential reference buffer creates positive and
negative reference voltages, REFT and REFB, respectively, that
define the span of the ADC core. The output common mode of
the reference buffer is set to midsupply, and the REFT and
REFB voltages and span are defined as follows:
REFT
AVDD
=
(
=
(
=
×
(
2
It can be seen from the equations above that the
REFT
and
REFB
voltages are symmetrical about the midsupply voltage
and, by definition, the input span is twice the value of the
VREF voltage.
VREF
REFB
AVDD VREF
Span
REFT
REFB
VREF
+
)
)
)
=
×
1 2
1 2
2
COMMON-MODE LEVEL (V)
S
90
85
75
70
65
50
80
0.0
55
60
0.5
1.0
1.5
2.0
2.5
3.0
T
–90
–85
–80
–75
–70
–65
–60
–55
–50
SNR 35MHz 2V DIFF
THD 35MHz 2V DIFF
THD 2.5MHz 2V DIFF
SNR 2.5MHz 2V DIFF
Figure 7. AD9235-65: SNR, THD vs. Common-Mode Level
The internal voltage reference can be pin-strapped to fixed values
of 0.5 V or 1.0 V, or adjusted within the same range as discussed
in the Internal Reference Connection
section. Maximum SNR
performance will be achieved with the AD9235 set to the largest
input span of 2 V p-p. The relative SNR degradation will be 3 dB
when changing from 2 V p-p mode to 1 V p-p mode.
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