參數(shù)資料
型號： AD9235BRUZRL7-65
廠商： Analog Devices Inc
文件頁數(shù)： 34/40頁
文件大小： 0K
描述： IC ADC 12BIT SGL 65MSPS 28TSSOP
標(biāo)準(zhǔn)包裝： 1,000
位數(shù)： 12
采樣率（每秒）： 65M
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 3
功率耗散（最大）： 300mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 28-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 28-TSSOP
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 2 個(gè)單端，單極；1 個(gè)差分，單極
AD9235
Data Sheet
Rev. D | Page 4 of 40
DIGITAL SPECIFICATIONS
Table 2.
Parameter
Temp
Test
Level
AD9235BRU/BCP-20
AD9235BRU/BCP-40
AD9235BRU/BCP-65
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
LOGIC INPUTS
High Level Input Voltage
Full
IV
2.0
V
Low Level Input Voltage
Full
IV
0.8
V
High Level Input Current
Full
IV
–10
+10
–10
+10
–10
+10
A
Low Level Input Current
Full
IV
–10
+10
–10
+10
–10
+10
A
Input Capacitance
Full
V
2
pF
LOGIC OUTPUTS1
DRVDD = 3.3 V
High-Level Output Voltage
Full
IV
3.29
V
(IOH = 50 A)
High-Level Output Voltage
Full
IV
3.25
V
(IOH = 0.5 mA)
Low-Level Output Voltage
Full
IV
0.2
V
(IOL = 1.6 mA)
Low-Level Output Voltage
Full
IV
0.05
V
(IOL = 50 A)
DRVDD = 2.5 V
High-Level Output Voltage
Full
IV
2.49
V
(IOH = 50 A)
High-Level Output Voltage
Full
IV
2.45
V
(IOH = 0.5 mA)
Low-Level Output Voltage
Full
IV
0.2
V
(IOL = 1.6 mA)
Low-Level Output Voltage
Full
IV
0.05
V
(IOL = 50 A)
1
Output voltage levels measured with 5 pF load on each output.
SWITCHING SPECIFICATIONS
Table 3.
Parameter
Temp
Test
Level
AD9235BRU/BCP-20
AD9235BRU/BCP-40
AD9235BRU/BCP-65
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
CLOCK INPUT PARAMETERS
Maximum Conversion Rate
Full
VI
20
40
65
MSPS
Minimum Conversion Rate
Full
V
1
MSPS
CLK Period
Full
V
50.0
25.0
15.4
ns
CLK Pulse-Width High1
Full
V
15.0
8.8
6.2
ns
CLK Pulse-Width Low1
Full
V
15.0
8.8
6.2
ns
DATA OUTPUT PARAMETERS
Output Delay2 (tPD)
Full
V
3.5
ns
Pipeline Delay (Latency)
Full
V
7
Cycles
Aperture Delay (tA)
Full
V
1.0
ns
Aperture Uncertainty Jitter (tJ)
Full
V
0.5
ps rms
Wake-Up Time3
Full
V
3.0
ms
OUT-OF-RANGE RECOVERY TIME
Full
V
1
2
Cycles
1
For the AD9235-65 model only, with duty cycle stabilizer enabled. DCS function not applicable for -20 and -40 models.
2
Output delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load on each output.
3
Wake-up time is dependent on value of decoupling capacitors; typical values shown with 0.1 F and 10 F capacitors on REFT and REFB.
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