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參數(shù)資料
| 型號： | AD9236BRUZRL7-80 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 12-Bit, 80 MSPS, 3V A/D Converter |
| 中文描述： | 1-CH 12-BIT FLASH METHOD ADC, PARALLEL ACCESS, PDSO28 |
| 封裝： | LEAD FREE, MO-153AE, TSSOP-28 |
| 文件頁數(shù)： | 17/36頁 |
| 文件大?。?/td> | 2056K |
| 代理商： | AD9236BRUZRL7-80 |
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AD9236
TIMING
The AD9236 provides latched data outputs with a pipeline delay
of seven clock cycles. Data outputs are available one propaga-
tion delay (t
PD
) after the rising edge of the clock signal. Refer to
for a detailed timing diagram.
Figure 2
The length of the output data lines and the loads placed on
them should be minimized to reduce transients within the
AD9236. These transients can degrade the converter’s dynamic
performance.
The lowest typical conversion rate of the AD9236 is 1 MSPS. At
clock rates below 1 MSPS, dynamic performance may degrade.
VOLTAGE REFERENCE
A stable and accurate 0.5 V voltage reference is built into the
AD9236. The input range can be adjusted by varying the refer-
ence voltage applied to the AD9236 using either the internal
reference or an externally applied reference voltage. The input
span of the ADC tracks reference voltage changes linearly. The
various reference modes are summarized in
described in the following sections.
and
Table 9
Table 9
Table 9. Reference Configuration Summary
Selected Mode
External Reference
Internal Fixed Reference
Programmable Reference
If the ADC is being driven differentially through a transformer,
the reference voltage can be used to bias the center tap (com-
mon-mode voltage).
INTERNAL REFERENCE CONNECTION
A comparator within the AD9236 detects the potential at the
SENSE pin and configures the reference into four possible
states, which are summarized in
the reference amplifier switch is connected to the internal resis-
tor divider (see
), setting VREF to 1 V. Connecting the
SENSE pin to VREF switches the reference amplifier output to
the SENSE pin, completing the loop and providing a 0.5 V ref-
erence output. If a resistor divider is connected as shown in
, the switch is again set to the SENSE pin. This puts the
reference amplifier in a noninverting mode with the VREF out-
put defined as follows:
. If SENSE is grounded,
Figure 33
Figure 33. Internal Reference Configuration
Figure 35
1
×
=
R1
R2
VREF
5
In all reference configurations, REFT and REFB drive the A/D
conversion core and establish its input span. The input range of
the ADC always equals twice the voltage at the reference pin for
either an internal or an external reference.
03066-A-017
10
μ
F+
0.1
μ
F
VREF
SENSE
0.5V
AD9236
VIN–
VIN+
REFT
0.1
μ
F
0.1
μ
F
10
μ
F
0.1
μ
F
REFB
SELECT
LOGIC
ADC
CORE
+
If the internal reference of the AD9236 is used to drive multiple
converters to improve gain matching, the loading of the refer-
ence by the other converters must be considered. F
depicts how the internal reference voltage is affected by loading.
igure 34
Figure 34. VREF Accuracy vs. Load
LOAD (mA)
E
0.05
0
0.5
1.0
1.5
2.0
2.5
3.0
03066-0-019
0
–0.25
–0.20
–0.15
–0.10
–0.05
0.5V ERROR (%)
1.0V ERROR (%)
SENSE Voltage
AVDD
VREF
0.2 V to VREF
Internal Switch
Position
N/A
SENSE
SENSE
Resulting VREF (V)
N/A
0.5
+
×
1
5
Resulting Differential
Span (V p-p)
2 × External Reference
1.0
2 × VREF
R1
R2
(See Figure 35)
Internal Fixed Reference
AGND to 0.2 V
Internal Divider
1.0
2.0
Rev. A | Page 17 of 36
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