參數(shù)資料
型號(hào)： AD9237BCPZ-65
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 13/24頁(yè)
文件大小： 0K
描述： IC ADC 12BIT SGL 65MSPS 32LFCSP
產(chǎn)品變化通告： Product Discontinuance 27/Oct/2011
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 12
采樣率（每秒）： 65M
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 3
功率耗散（最大）： 190mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP-VQ（5x5）
包裝： 托盤
輸入數(shù)目和類型： 2 個(gè)單端，單極；1 個(gè)差分，單極
AD9237
Data Sheet
Rev. B | Page 20 of 24
This maximum current occurs when every output bit switches
on every clock cycle, that is, a full-scale square wave at the
Nyquist frequency, fCLK/2. In practice, the DRVDD current is
established by the average number of output bits switching,
which is determined by the encode rate and the characteristics
of the analog input signal.
SAMPLE RATE (MSPS)
POWER
(mW)
190
170
150
130
110
90
70
10
60
65
50
40
30
20
05455-047
AD9237-65
AD9237-40
AD9237-20
Figure 43. Total Power vs. Sample Rate with fIN = 10 MHz
For the AD9237-20 speed grade, the digital power consumption
can represent as much as 10% of the total dissipation. Digital
power consumption can be minimized by reducing the
capacitive load presented to the output drivers. The data in
Figure 43 was taken with a 5 pF load on each output driver.
The AD9237 is designed to provide excellent performance with
minimum power. The analog circuitry is optimally biased so
that each speed grade provides excellent performance while
affording reduced power consumption. Each speed grade
dissipates a baseline power at low sample rates that increases
linearly with the clock frequency, as shown in Figure 43.
The power scaling feature provides an additional power savings
when enabled, as shown in Figure 44. The power scaling mode
cannot be enabled if the clock is varied during operation. This is
because the internal circuitry cannot quickly track a changing
clock, and the part does not have enough power to operate
properly.
SAMPLE RATE (MSPS)
POWER
(mW)
190
170
150
130
110
90
70
10
60
65
50
40
30
20
05455-096
AD9237-65
AD9237-40
AD9237-20
Figure 44. Total Power vs. Sample Rate with Power Scaling Enabled
The MODE2 pin is a multilevel input that controls the span
factor and power scaling modes. The MODE2 pin is internally
pulled down to AGND by a 70 k resistor. The input threshold
and corresponding mode selections are outlined in Table 8.
Table 8. MODE2 Selection
MODE2 Voltage
Span Factor
Power Scaling
AVDD
1
Disabled
2/3 AVDD
1
Enabled
1/3 AVDD
2
Enabled
AGND (Default)
2
Disabled
The PDWN pin is a multilevel input that controls the power
states. The input threshold values and corresponding power
states are outlined in Table 9.
Table 9. PDWN Selection
PDWN Voltage
Power State
Power (mW)
AVDD
Power-Down Mode
1
1/3 AVDD
Standby Mode
20
AGND (Default)
Normal Operation
Based on speed grade
By asserting the PDWN pin high, the AD9237 is placed in
power-down mode. In this state, the ADC typically dissipates
1 mW. During power-down, the output drivers are placed in a
high impedance state. Low power dissipation in power-down
mode is achieved by shutting down the reference, reference
buffer, biasing networks, clock, and duty cycle stabilizer
circuitry. The decoupling capacitors on REFT and REFB are
discharged when entering power-down mode and then must
be recharged when returning to normal operation.
As a result, the wake-up time is related to the time spent
in power-down mode and shorter standby cycles result in
proportionally shorter wake-up times. With the recommended
0.1 F and 10 F decoupling capacitors on REFT and REFB, it
takes approximately 1 sec to fully discharge the reference buffer
decoupling capacitors and 3 ms to restore full operation.
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