參數(shù)資料
型號(hào)： AD9238BCPZRL-40
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 28/48頁(yè)
文件大小： 0K
描述： IC ADC 12BIT DUAL 40MSPS 64LFCSP
標(biāo)準(zhǔn)包裝： 2,500
位數(shù)： 12
采樣率（每秒）： 40M
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 330mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 4 個(gè)單端，單極；2 個(gè)差分，單極
配用： AD9238BCP-65EBZ-ND - BOARD EVAL WITH AD9238BCP-65
AD9238
Rev. C | Page 34 of 48
DUAL ADC LFCSP PCB
The LFCSP PCB requires a low jitter clock source, analog sources,
and power supplies. The PCB interfaces directly with Analog
Devices standard dual-channel data capture board (HSC-ADC-
EVAL-DC), which together with ADI’s ADC Analyzer software
allows for quick ADC evaluation.
POWER CONNECTOR
Power is supplied to the board via three detachable 4-lead
power strips.
Table 11. Power Connector
Terminal
Comments
Analog supply for ADC
Output supply for ADC
Supply circuitry
VREF
Optional external VREF
+5 V
Optional op amp supply
5 V
Optional op amp supply
1VCC, VDD, and VDL are the minimum required power connections.
ANALOG INPUTS
The evaluation board accepts a 2 V p-p analog input signal
centered at ground at two SMB connectors, Input A and
Input B. These signals are terminated at their respective
transformer primary side. T1 and T2 are wideband RF
transformers that provide the single-ended-to-differential
conversion, allowing the ADC to be driven differentially,
minimizing even-order harmonics. The analog signals can be
low-pass filtered at the transformer secondary to reduce high
frequency aliasing.
OPTIONAL OPERATIONAL AMPLIFIER
The PCB has been designed to accommodate an optional
AD8139 op amp that can serve as a convenient solution for
dc-coupled applications. To use the AD8139 op amp, remove
C14, R4, R5, C13, R37, and R36. Place R22, R23, R30, and R24.
CLOCK
The clock inputs are buffered on the board at U5 and U6. These
gates provide buffered clocks to the on-board latches, U2 and
U4, ADC input clocks, and DRA and DRB that are available at
the output Connector P3, P8. The clocks can be inverted at the
timing jumpers labeled with the respective clocks. The clock
paths also provide for various termination options. The ADC
input clocks can be set to bypass the buffers at P2 to P9 and
P10, P12. An optional clock buffer U3, U7 can also be placed.
The clock inputs can be bridged at TIEA, TIEB (R20, R40) to
allow one to clock both channels from one clock source; however,
optimal performance is obtained by driving J2 and J3.
Table 12. Jumpers
Terminal
Comments
OEB A
Output Enable for A Side
PDWN A
Power-Down A
MUX
Mux Input
SHARED REF
Shared Reference Input
DR A
Invert DR A
LATA
Invert A Latch Clock
ENC A
Invert Encode A
OEB B
Output Enable for B Side
PDWN B
Power-Down B
DFS
Data Format Select
SHARED REF
Shared Reference Input
DR B
Invert DR B
LATB
Invert B Latch Clock
ENC B
Invert Encode B
VOLTAGE REFERENCE
The ADC SENSE pin is brought out to E41, and the internal
reference mode is selected by placing a jumper from E41 to
ground (E27). External reference mode is selected by placing a
jumper from E41 to E25 and E30 to E2. R56 and R45 allow for
programmable reference mode selection.
DATA OUTPUTS
The ADC outputs are latched on the PCB at U2 and U4. The
ADC outputs have the recommended series resistors in line to
limit switching transient effects on ADC performance.
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