參數(shù)資料
型號(hào): AD9240ASZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 3/24頁(yè)
文件大小: 0K
描述: IC ADC 14BIT 10MSPS 44-MQFP
標(biāo)準(zhǔn)包裝: 1
位數(shù): 14
采樣率(每秒): 10M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 7
功率耗散(最大): 330mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 44-QFP
供應(yīng)商設(shè)備封裝: 44-MQFP(10x10)
包裝: 托盤
輸入數(shù)目和類型: 2 個(gè)單端,單極;1 個(gè)差分,單極
產(chǎn)品目錄頁(yè)面: 780 (CN2011-ZH PDF)
AD9240
REV.
–11–
Table I. Analog Input Configuration Summary
Input
Input Range (V)
Figure
Connection
Coupling
Span (V)
VINA
1
VINB
1
#
Comments
Single-Ended
DC
2
0 to 2
1
32, 33
Best for stepped input response applications, suboptimum THD
and noise performance, requires
±5 V op amp.
2
× VREF
0 to
VREF
32, 33
Same as above but with improved noise performance due to
2
× VREF
increase in dynamic range. Headroom/settling time requirements
of
±5 V op amp should be evaluated.
5
0 to 5
2.5
32, 33
Optimum noise performance, excellent THD performance. Requires
op amp with VCC > +5 V due to insufficient headroom @ 5 V.
2
× VREF
2.5 – VREF
2.5
39
Optimum THD performance with VREF = 1, noise performance
to
improves while THD performance degrades as VREF increases
2.5 + VREF
to 2.5 V. Single supply operation (i.e., +5 V) for many op amps.
Single-Ended
AC
2 or
0 to 1 or
1 or VREF
34
Suboptimum ac performance due to input common-mode level
2
× VREF
0 to 2
× VREF
not biased at optimum midsupply level (i.e., 2.5 V).
5
0 to 5
2.5
34
Optimum noise performance, excellent THD performance.
2
× VREF
2.5 – VREF
2.5
35
Flexible input range, Optimum THD performance with VREF = 1.
to
Noise performance improves while THD performance degrades as
2.5 + VREF
VREF increases to 2.5 V.
Differential
AC or
2
2 to 3
3 to 2
29–31
Optimum full-scale THD and SFDR performance well beyond the
DC
A/Ds Nyquist frequency.
2
× VREF
2.5 – VREF/2
2.5 + VREF/2
29–31
Same as 2 V to 3 V input range with the exception that full-scale
to
THD and SFDR performance can be traded off for better noise
2.5 + VREF/2
2.5 – VREF/2
performance.
5
1.25 to 3.75
3.75 to 1.25
29–31
Widest dynamic range (i.e., ENOBs) due to optimum noise
performance.
1VINA and VINB can be interchanged if signal inversion is required.
Table II. Reference Configuration Summary
Reference
Input Span (VINA–VINB)
Operating Mode
(V p-p)
Required VREF (V)
Connect
To
INTERNAL
2
1
SENSE
VREF
INTERNAL
5
2.5
SENSE
REFCOM
INTERNAL
2
≤ SPAN ≤ 5 AND
1
≤ VREF ≤ 2.5 AND
R1
VREF AND SENSE
SPAN = 2
× VREF
VREF = (1 + R1/R2)
R2
SENSE AND REFCOM
EXTERNAL
2
≤ SPAN ≤ 51 ≤ VREF ≤ 2.5
SENSE
AVDD
(NONDYNAMIC)
VREF
EXT. REF.
EXTERNAL
2
≤ SPAN ≤ 5
CAPT and CAPB
SENSE
AVDD
(DYNAMIC)
Externally Driven
VREF
REFCOM
EXT. REF. 1
CAPT
EXT. REF. 2
CAPB
B
相關(guān)PDF資料
PDF描述
VI-J1L-MW-F4 CONVERTER MOD DC/DC 28V 100W
VE-B1L-MX-F3 CONVERTER MOD DC/DC 28V 75W
AD7712ARZ IC ADC SIGNAL COND LC2MOS 24SOIC
MAX13433EETD+T TXRX RS-485 16MBPS FULL 14TDFN
LTC1609CSW#PBF IC ADC SRL 16BIT 200KSPS 20-SOIC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9240ASZRL 功能描述:IC ADC 14BIT 10MSPS 44-MQFP TR RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率(每秒):83k 數(shù)據(jù)接口:串行,并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散(最大):95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP(0.600",15.24mm) 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個(gè)單端,雙極
AD9240EB 制造商:AD 制造商全稱:Analog Devices 功能描述:Complete 14-Bit, 10 MSPS Monolithic A/D Converter
AD9240-EB 制造商:Analog Devices 功能描述:
AD9241 制造商:AD 制造商全稱:Analog Devices 功能描述:Complete 14-Bit, 1.25 MSPS Monolithic A/D Converter
AD9241ACHIPS 制造商:Analog Devices 功能描述: